ALTMEMPHY - No Clocks - RefClk Slew Rate Requirements?

I'm debugging a Cyclone IV E design. The DDR2 interface is dead in hardware but simulates okay. Signaltap shows two out of three DIMM clocks dead. I scoped the 50 MHz reference clock and the rise and fall times are larger than the high and low time (about 5ns each). The external oscillator drives six (!) clock inputs so rather heavily loaded.

Would an ALTPLL instance have trouble locking onto a reference clock with too low slew rate? I have not been able to find any official information directly from the Altera documentation.

Also, the engineer has incorrectly assigned the clock locations. The positive and negative signals in the pairs are not in adjacent locations giving these warnings in Quartus II:

Warning (176684): Unable to place CK/CKn pair mem_clk[2] and mem_clk_n[2] on a differential pin pair because they have been assigned to incompatible pins not belonging in the same pair
Warning (176684): Unable to place CK/CKn pair mem_clk[1] and mem_clk_n[1] on a differential pin pair because they have been assigned to incompatible pins not belonging in the same pair
Warning (176684): Unable to place CK/CKn pair mem_clk[0] and mem_clk_n[0] on a differential pin pair because they have been assigned to incompatible pins not belonging in the same pair

I'm trying to figure out if the current board can be made to work or if the engineer has to re-spin the board with corrected clock locations.

Thanks!

Attached Images

• 50 MHz Clock (p38).jpg (128.7 KB)