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ALTMEMPHY - No Clocks - RefClk Slew Rate Requirements?
I'm debugging a Cyclone IV E design. The DDR2 interface is dead in hardware but simulates okay. Signaltap shows two out of three DIMM clocks dead. I scoped the 50 MHz reference clock and the rise and...
View Articledriver request
I wish to use the window Jungo driver that to work with my cyclone V board. Where can I download those drivers and usage manual?
View ArticleYocto BSP layer for Arria10 ARM
Hello: Does anyone have the Yocto BSP layer for the Arria10 SoC? The instructions from RocketBoards don't seem to work. Thank you, -Ilya.
View ArticlePoky yocto BSL layer for Arria10
Hello: Anyone has/knows the BSP layer for Arria10 for Yocto 1.8. The instructions on the RocketBoards aren't really working (at all) and for this chip in particular.
View ArticleDesign Use 24bit AUDIO CODEC on kit DE1
Hello! I just design a module to read data analog from line in audio to ADC of WM8731 and use FIFO altera to transmit data to DAC, then analog from DAC transmit to line out. I want test AUDIO CODEC,but...
View ArticleSimple DDR input in Cyclone V
After spending the better part of the day RTFM, I have to ask: Is there a simple way, that does not involve using the MegaWizard to create an ALTLVDS_RX, to implement a DDR input in a Cyclone V device?...
View Articleturning off and on the two 7 segment --- help
hi, I need help with quartus II 9 I should create two verilog files : 1. turn off 2. turn on two 7 segments that display in Altera FPGA's boards I tried some codes in the net but it's not working :( I...
View Articlehps to fgpa or fpga to hps example use case
Hi, i am new here, i read the cyclone V hand book related with the bridge for access the SD RAM either for hps direction or fpga direction, i can see that the pre build golden reference is already...
View ArticleReplace the GHRD SD MMC to be a smaller EMMC chip?
Hi, Any precaution for us to replace the current SD MMC slot to another eMMC slot? is the communication is compatible all the way?
View Articlehps boot from fpga
I read the pages mentioned that boot from sd card and qspi is relatively about the same file structure, but if boot from fgpa, it is only able to place the uboot in the fpga and the rest of the boot...
View ArticleModelsim simulation in Quartus II
I am trying to simulate using Modelsim in Altera Lite environment. I entered in the Tools directory the location of the Modelsim executable, which also has the file "student_license_dat", a valid...
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How match two bus in one
Hi, I need match the two bus, to got 32 bits in the end Isn't working, "12009 Node "Novo[x]" is missing source" Where's the problem? Thanks very much Attached Images Quartus.png (6.4 KB)
View ArticleUsing ADC with HPS on DE1-SoC Board
Hello all, I am currently trying to connect the ADC with the HPS on the DE1-SoC board. I am able to write programs to control the LEDS via the HPS, however, I am having some trouble getting the adc to...
View ArticleAltera DE1 cyclone ii send serial data to laptop via rs232
Hello and good day all. I just buy Altera DE1 cyclone ii EP2C20F484C7. Have done playing some basic example using Quartus II 13.0sp1 Web Edition. Is there any example for sending serial data through...
View ArticleUsing De2-115 board to run a project developed on a different board ?
Hi, I am trying to run different open source projects/games on my DE2-115 Altera board, however, these projects are usually developed on different boards like: Xilinx Spartan 3, DE0, DE1, ...etc. My...
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how to use set false path properly to constrain clocks in different clock...
IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC in...
View ArticleNios II boot from qspi
Do we have clearer guide how to boot nios II from qspi? i read the an 730 but there are some area which is still remain unclear.
View Articleopen CL hardware requirement
Reading the open CL guide where there is some description mention for the hardware host requirement for development purpose only , but not really stating the running hardware requirement. Is that mean...
View ArticleDownloading an OpenCL Design Example link down
Any alternative link i can download the open cl examples?
View Articleuniphy DDR parameter reading from datasheet guide
Hi, i am new here, i am designing a device that is using the DDR3 with a uniphy interconnection. But i notice there is a lot of parameter that i not sure and wish to confirm. example such as sped...
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