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About Manual Logic Duplication
Hi, I edit Assignment Editor as follows. Code: Ok  sysstate  datatouart  Manual Logic Duplication  sysstate_mld  Yes  top After placing and routing, I started TimeQuest and then double...
View ArticleThere is no Cyclone IV Net Length Report, why? Whos has it?
In the web: https://www.altera.com/support/suppo...-and-Libraries there is no Cyclone IV Net Length Information. Why? Whos has it? I deign with the Cycline IV GX chips of EP4CGX150F27. Thanks!
View ArticleAOCL Diagnostic problem: cannot find the upstream slot
Hello forum! I have a problem with using DE5_NET board. Afted installation Quartus, AOCL SDK, BSP and setting Env variables i try diagnose board. "aocl diagnose: Running diagnostic from...
View ArticleVHDL Code Help
Hi everyone, I'm new FPG and VHDL, I am trying write this code: Pushing a SW1 will turn on the 4 LEDs on the board one by one from up to down every 2 seconds until all LEDs are lit and the process...
View Articlequartus ii internal error: Sub-system: ECOQ
When I opened Quartus II(version 14.1)，there occurs one error, whose description is below: "Problem Details Error: Internal Error: Sub-system: ECOQ, File: /quartus/ace/ecoq/ecoq_manager.cpp, Line: 179...
View Articleon chip termination for LVDS Signals in Arria V GX FPGA
How to enable on chip termination of 100 ohms (RD) for LVDS Signals in Arria-V GX FPGA.
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Implemention of JAL to Mips Datapath
Hi I want to make the MIPS support JAL instruction, I made this way , the project compiles, the implement of Jump I'm very sure it's working properly, but the JAL after the simulation doesn't result in...
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Maximum avaliable frequency with the altera_gpio at Arria 10
Hello! I try to create very simple DDR register with help of AlteraGPIO megafunction. This project must generate clock (200 MHz) and periodical data pulse at rising edge of clock, which has 90 degree...
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DE0-NANO and Qsys : error when quit Qsys tools
Hi, I begin to use Quartus 15.0 and Qsys. I want create a ADC project. I use Qsys tools. I put CPU : Nios II (Classic) Processor. When I quit Qsys tools, i have this error (I didn't generate): I try to...
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[HPS] Peripherals Mux Table -> How to use?
Hi All, I need some clarification regarding the Peripherals Mux Table usage. How should I understand it? Is the First Column the Mux Output? Are the next columns the Mux Inputs? If so, let's consider...
View ArticleData in matrix form
Hi guys. I have data which is in matrix 2D. I want to used the data for my memory which is lpm rom. I save tha data in .mif file. So now I am curious about the the number of words and word size. My...
View ArticleLoad Kernel module in DE1-SoC Linux Ubuntu
Hello, I am using Terasic DE1-SoC development board. The operative System's image stored in the SD card is Linux Ubuntu Desktop. The system boots alright. However, I cannot load a kernel module I need...
View ArticleVHDL Help Requested
Hello. I'm a VHDL newbie and request help on coding a counter. I'm trying to synchronize a BTRIG signal to the system clock and then toggle a short_long_sample_q signal every 4 synchronized BTRIG...
View ArticleNeed help for LVDS deserializer
Hello, I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's. I develop from Quartus II, and I...
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PWM with different duty cycles
I am currently working on Pwm. i am able to generate one duty cycle. but my code is not taking the lookup cycle. what exactly we are trying to do is. create PWM with different duty cycle. fed the...
View ArticleMAX10 FPGA on-chip memory size question
Hi, in the datasheet of the MAX10 FPGA type10M50DAF484C8GES I read that the on-chip memory has a size of 1,677,312 kbits. This means a size of more than 209 MBye. This seems to be extremely large. Is...
View ArticleStratix 10 Datasheet
Hello, I checked the website and i don't find the technical document of stratix 10, is it not ready? Please, Can anyone help me to find this document? Thanks in advance
View ArticleAltera_fp_functions
Hello, I am trying to instantiate the altera_fp_functions ip core into my design and I have included the libraries necessary. i.e library altera_mf; use altera_mf.altera_mf_components.all; The name I...
View ArticleRunning power analyser without using a test bench
I have a very self contained program ( the input data is preloaded using MIF files into block ram, processed and the output is again stored in block RAM ). the only ports to my program are clock, reset...
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Timing analysis error: Modelsim error vsim-3039
I have an 8b counter for learning timing analysis. I have completed Fitter, Assember, Timequest and EDA Netlist without any error. I have added the sdc file to the Assignment. When I run the gate level...
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