VHDL Help Requested

Hello. I'm a VHDL newbie and request help on coding a counter. I'm trying to synchronize a BTRIG signal to the system clock and then toggle a short_long_sample_q signal every 4 synchronized BTRIG pulses. Here's the applicable section of code:

process ( SYS_CLK )
begin
if rising_edge ( SYS_CLK ) then
temp_pulse <= BTRIG ;
btrig_synched <= temp_pulse ;
end if ;
end process ;

process ( btrig_synched )
begin
if rising_edge ( btrig_synched ) then
btrig_counter <= btrig_counter + 1 ;
end if ;
end process ;

process ( btrig_counter , short_long_sample_q )
begin
if btrig_counter = "11" then
short_long_sample_q <= not short_long_sample_q ;
end if ;
end process ;


I don't get any compile errors but the tested behavior shows that short_long_sample_q does not consistently toggle every 4 BTRIGs. Is there a better way of coding this? Thanks.