Simple DDR input in Cyclone V

After spending the better part of the day RTFM, I have to ask:

Is there a simple way, that does not involve using the MegaWizard to create an ALTLVDS_RX, to implement a DDR input in a Cyclone V device? I mean, something as simple as Xilinx' IDDR2 primitive.

I have a source which provides some DDR data bits and a synchronous clock, and all I need to do is to capture the bits in the input and present two outputs (one rising edge, one falling edge) per data bit.

This should be incredibly simple ....

Thanks.