IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC in my project, which is drived by ADC_CLK. c1 is one output clock of pll,named ADC_CLK_x2. It's frequency is 96MHz.c1 is the main signal processing clock in other entities.
Then I compiled my project, it says that the setup time slack of c1 is negative. I see the worst-case timing paths.I find that the launch clock is CLK_In_50MHz ,and the latch clock is c1. I konw that it this two clocks are considered relative when it compiling. I used set false paths commond in my sdc file. But it didn't work. I don't know whether I use it correctly or not. In my sdc file, i_PLL_ADC|altpll_component|auto_generated|pll|clk[1] is the clock name of c1,which is one output of pll. I don't know whether I can use this name in set false paths commond or not.
My tcl file and worst-case timing paths are attached.
Someone can help me?
Then I compiled my project, it says that the setup time slack of c1 is negative. I see the worst-case timing paths.I find that the launch clock is CLK_In_50MHz ,and the latch clock is c1. I konw that it this two clocks are considered relative when it compiling. I used set false paths commond in my sdc file. But it didn't work. I don't know whether I use it correctly or not. In my sdc file, i_PLL_ADC|altpll_component|auto_generated|pll|clk[1] is the clock name of c1,which is one output of pll. I don't know whether I can use this name in set false paths commond or not.
My tcl file and worst-case timing paths are attached.
Someone can help me?