Hi,
I'm using the latest version of Quartus (12.1 with sp1) and a number of LPM dividers in a Cyclone 3 FPGA design (plus other LPMs, RAMs, PLLs, VHDL modules, etc.,). The dividers in question all have the same clock but are in different modules with completely different phasing (divide is started by different events). Numerators and denominators for different dividers come from different places.
Quartus synthesis gives warning and information but completes successfully.
However in the Worst-Case Timing Paths results I get reports of timing issues between RAMs of one divider and the pipeline registers of another even if they are in different data paths. It's easy enough to get rid of them using set_false_path in the .sdc constraint file but my question is why is TimeQuest finding these data paths which appear to me to be non-existant?
An example of this is-
entity_ir:comp_ir|sp_09:divide_resp|lpm_divide:lpm _divide_component|lpm_divide_8kr:auto_generated|si gn_div_unsign_6sh:divider|alt_u_div_plg:divider|al tshift_taps:DFFQuotient_rtl_1|shift_taps_a1q:auto_ generated|altsyncram_mh81:altsyncram2|ram_block3a7
to
entity_ir:comp_ir|e_hist:hist|e_plat_div:c_plat_di v|lpm_divide:LPM_DIVIDE_component|lpm_divide_n2s:a uto_generated|sign_div_unsign_lai:divider|alt_u_di v_rtf:divider|DFFStage[182]
My first posting on the Altera Forum (normally able to resolve issues myself or use the Altera support), any comments on things I've not got right gratefully received.
I'm using the latest version of Quartus (12.1 with sp1) and a number of LPM dividers in a Cyclone 3 FPGA design (plus other LPMs, RAMs, PLLs, VHDL modules, etc.,). The dividers in question all have the same clock but are in different modules with completely different phasing (divide is started by different events). Numerators and denominators for different dividers come from different places.
Quartus synthesis gives warning and information but completes successfully.
However in the Worst-Case Timing Paths results I get reports of timing issues between RAMs of one divider and the pipeline registers of another even if they are in different data paths. It's easy enough to get rid of them using set_false_path in the .sdc constraint file but my question is why is TimeQuest finding these data paths which appear to me to be non-existant?
An example of this is-
entity_ir:comp_ir|sp_09:divide_resp|lpm_divide:lpm _divide_component|lpm_divide_8kr:auto_generated|si gn_div_unsign_6sh:divider|alt_u_div_plg:divider|al tshift_taps:DFFQuotient_rtl_1|shift_taps_a1q:auto_ generated|altsyncram_mh81:altsyncram2|ram_block3a7
to
entity_ir:comp_ir|e_hist:hist|e_plat_div:c_plat_di v|lpm_divide:LPM_DIVIDE_component|lpm_divide_n2s:a uto_generated|sign_div_unsign_lai:divider|alt_u_di v_rtf:divider|DFFStage[182]
My first posting on the Altera Forum (normally able to resolve issues myself or use the Altera support), any comments on things I've not got right gratefully received.