FIR filter design with IEEE 754 half-precision floating point

Hi All

We are in the initial phase of a project which implements processing of biomedical signals.
I am trying to implement FIR filter with IEEE 754 half-precision (16-bit) floating point arithmetic.

Please find my doubts below,

1. Major doubt is that, WILL the data format from the ADC to the FPGA (through I2C interface) be different from the data format which I try to implement?
OR any of you knows an ADC chip which produces the specific data format?

2. If I am not able to get an ADC which produces the specific data format, I would need to convert the format. Is this the way that is normally followed in FPGA implementations? (Sorry, I am new to FPGA implementations)

3. I decided to use this format since the biomedical signals are in the range (+/-1mV , after amplification). Please correct me if am totally wrong.

Thanks a lot for your replies.