FPGA instability after reset

Hi all,

I am working with a custom Cyclone IV E based HW that is suffering from strange startup instability.
The HW runs fine under various stress tests and temperature ranges when programmed through JTAG,
but if the FPGA configures from EPCS flash the main CPU (Nios2) will likely hang inside the bootloader
(running from internal RAM). If the bootloader code manages to complete the system will run fine. The
actual hang traces to SDRAM access - copying firmware code from EPCS to SDRAM. Interestingly
if after the hang SDRAM test program is downloaded through JTAG (w/ or w/o FPGA reconfiguration) it
will run without errors. Similarly the bootloader runs fine when programmed through JTAG.

The hang is more likely to occur when using the reset switch than at power on (reset switch is wired
to nCONFIG). The internal reset (CPU, ethernet Phy, PLLs, ...) is similar to 'global reset generator' used
in many Altera examples. But instead of one reset signal I use two, they assert simultaneousely and deassert
in sequence. The reset signal to deassert first goes to PLLs and the second to CPU, ... What I've found
is that the system instability is somehow related to PLLs reset. If I leave areset fixed to 0 than the system
is less likely to hang and if I increase the second reset time to ~100ms (first reset - PLLs - deaserts after 1ms)
the system doesn't hang. I am not comfortable with this workaround, since according to the datasheet max
PLL resync time is 1ms, beside the PLL locked signals are among my reset sources and I didn't see any
self reset during boot.

I could use some pointers. I didn't design the custom board I am using and it's not really my field, so
unfortunately I cannot give more details about the HW.

Thanks.