Hello everybody I have an issue with this one line of code here:
bit_field and output are 32 bit std_logic_vector
msbd and lsb are 5 bit std_logic_vectors
Issue is when I convert the VHDL file to a symbol file I get this:
Can some one tell me what the issue is?
Code:
output(to_integer(unsigned(msbd) + unsigned(lsb)) downto 0) <= bit_field(to_integer(unsigned(msbd) + unsigned(lsb)) downto to_integer(lsb));msbd and lsb are 5 bit std_logic_vectors
Issue is when I convert the VHDL file to a symbol file I get this:
Code:
Error (10405): VHDL error at aluvhdl_entities.vhd(896): can't determine type of object at or near identifier "to_integer" -- found 0 possible types