VHDL Noob - creating one octave monophonic synthesizer
I am working on a project for school and was wondering how do you go about creating a sound frequency in VHDL? I am using quartus II
View ArticleDDR3 Layout Length Matching
Hello, I am laying out a DDR3 memory based on 4x 16bit chips and have seen in EMI Handbook Vol 2, Chap 4, Table 4-23 that "data, address and command signals must have matched length traces to within...
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i need help with coursework
pleas take look in attachment. i need help and how i can start..... its 2 hard for me if u can help, i will be thankful , if u cant pleas dont write a complain Attached Files de3_4_general (5).doc...
View ArticleDe0 Nano ADC demo coding explanations
Hello everyone, there's a code line (below) I don't understand from the De0-Nano ADC demo. I tried to find out about the (?) but as far as I can get, there is only (?: conditional) in verilog syntax....
View ArticleNIOS-II program failed during execution
Hello everyone, I'm encountering a new failure in my application running on NIOS-II/e (DE-1 EP2C20). As my app grows (every time I add a new function), some parts of my app will go fail during run-time...
View Articleconvert an integer to a vector
I have a constant for eg. 5.Now i have to convert into vector form.How can i do it in vhdl code?I think there is no necessary to write a code in testbench for the waveform,because there is no need of...
View Articlesignal delay
hi,everyone, I want to make a signal event A to delay sometime according an other signal event B, that is, if sometime A happened, and after B happened C times, I can get a signal to trigger something....
View ArticleDE2 Booting from CFI
Hello everyone, I have a DE2 Cyclone 2 kit. Now, I want to update program from the nand flash and run it on RAM. After a feel day, I consulted from altera documents and read threads on Altera forum. I...
View ArticleRemote Update over PCI Express
Hi, I'm currently developing a device which is connected to a PC over PCIe. My device has a JTAG connector which is planned to be used for an initial programming. But when the Device is in its housing,...
View ArticleProblem using Compiled ALTERA Encrypted Megawizard IP into ModelSim
I have compiles Quartus V12.1 Native_Phy Megawizard IP using ModelSim 10.1d I got a list of numbers instead of names in the compiled directory. And a message of item "not bound" in the ModelSim screen....
View ArticleUsing the Alt4GXB in an Arria2GX (Quartus 11.1)
Somehow the documentation is incomplete or unclear regarding the Alt4GXB on a Arria2GX. One of the help pages asks me to use the MegaWizard to create the AltGXB. There, the actual parameters do not fit...
View ArticleFloating point custom instruction in nios2
To perform the floating point multiplication in the Floating Point Custom Instruction which is inbuilt, how should I pass the values from the nios code? Do I have to use a specific format for the...
View ArticleCustom component file locations in Qsys
I find that a lot of my IP isn't particularly re-usable; it'll have a very particular interfaces that communicate with some specific external hardware on one board, etc. That's fine; writing a...
View ArticlePCI express and NIOS
I had a NIOS system working with my custom peripheral this morning on the transceiver starter kit this morning. I then added a PCI express interface and had to modify the design a bit so I could fit...
View Articlespecifications of external clock signal DE2 Board and Starter Development Board
Hi, im trying to synchronize a comunication system with a 10MHz clock, for that, I'm using a PLL IC (MM74HC4046), then the main issue is that this IC gives 5 Volts signal, and after research of my...
View Articlequartus 2 and proteus plug in
hi all . As you already know such tools as ModelSim and Aldec are for verilog and VHDL simulation, there i can design my own microprocessor, or microcontroller and compile my verilog or VHDL code. but...
View ArticleNios using onchip memory resets continuously
I am using a small footprint EP4CE6 FPGA with NIOSII built using 20KB on chip memory. Using Eclipse IDE I built the "small hello world" example as a starting point. My problem is that when I add...
View ArticleIssue when converting between multiple data types
Hello everybody I have an issue with this one line of code here: Code: output(to_integer(unsigned(msbd) + unsigned(lsb)) downto 0) <= bit_field(to_integer(unsigned(msbd) + unsigned(lsb)) downto...
View ArticleVHDL "EVENT" Problem
Hello, I'm a beginner for using Quartus II. I have an error in this VHDL code -------------------------------------------------------------------------------------- library ieee; use...
View Articletest bench for d flip flop
I have write a code in vhdl for d flip flop as below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d_ff_en is Port ( clk : in...
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