Arria V 10GBase-R lane polarity inversion
What is the setting to invert the lane polarity of one tx lane coming out of Arria V GT device. I am running 10GbaseR Phy. It used to be pretty straightforward in Arria II and Stratix IV. But I am not...
View ArticleConfiguring FPGA through EPCS (EEPROM) INCLUDING Nios II program?
Hello people! I have made numerous VHDL applications where I configure the FPGA on boot via the EPCS (EEPROM) chip. So until now I know how to create a .jic file and save it to the EEPROM so that the...
View ArticlePlease help me for communication between FPGA and desktops computer
I am new for FPGA designing. I bought a board -- Arrows SoCKIT Solution Accelerates ARM-Based SoC Design(http://www.altera.com/b/arrow-sockit.html). However,I have no idea how to use C language...
View ArticleRequire software tool for Ethernet frame analyzer
Hi, I am current working on Ethernet protocol. Do anyone know any software tool for sending and receiving Ethernet frames? For example: If i send ethernet frame from my custom FPGA Board to my PC, i...
View ArticleDev.kit with gigabit ethernet
Hello all, could you advice me some development kit with gigabit ethernet PHY ? I need quickly send data from fpga on-chip ram to pc and when i use 10/100Mb PHY DP83848 i achieve max. 6-7MB/s data flow...
View ArticleAre the IP cores form the University Program (USB, Ethernet) available in VHDL?
Hello all! My question is whether the implementation in VHDL of the IP cores (Ethernet, USB, LCD, etc.) used in the Qsys examples of the University Program are available. I would imagine that there is...
View ArticleDebugging PC Express hard IP core
Hi all, I've got a link up (ltssmstate = L0) - and external device sees the link but still I don't see any data going out from hard IP core. How can I debug and see whether anything is coming to Hard...
View ArticleOrdering of Ports for exported Qsys signal conduits
Hi, I have a design with a Qsys that is slowley growing. I find that each time I export another signal conduit it gets added to the bottom of the component. This is the same for the generated VHDL...
View ArticleClik here to view.
BSP-editor not generating Makefile and preloader.ds
Hi guys, I get this error: - DERIVED_RESET_ASSERT_HPS2FPGA: not such variable when trying to "generate" from BSP-editor as described in "SoCKit_SW_LAB_13.0" (exactly following guidelines...). This...
View ArticleStratix iv EP4SGX530F device experiencing high speed failures with loop back...
We are manufacturing a board with a ep4sgx530nf45c2n Stratix IV device and our customer is experiencing 50% failures while conducting a loopback speed test. The failures are occurring at around 80...
View ArticleMAX II CPLD Selection for Encoder
Dear all, I am new to CPLD here. I want to use a CPLD MAXII (3.3V) EPM240 to realize a 20 key encoder. Does anyone know if MAXII is recommended to new design? If EPM240 is enough to realize this...
View ArticleQsys : Arria V: PCIe Avalon ST source to SGDMA Avalon ST sink interconnect error
Hi I have configured a PCIe Hard IP for X4 Gen 2 har macro with Avalon streaming interface. This necessitates a Avalon ST - 128 bit application interface. In trying to connect the Avalon ST tx, to the...
View ArticleRSA Public/Private Key Cryptography
I'm working on a project with a Cyclone IV, using Micrium uC/OS-II and part of this process involves RSA Public/Private Key Cryptography. Basically I have an encrypted message (128-bit RSA) that needs...
View ArticleClik here to view.
Hello, whats product in the photo?
Hello, whats product in the photo? 图片1.jpg Attached Images 图片1.jpg (8.3 KB)
View ArticleQuestion about Sockit board communicating with PC
I am new in FPGA design. I want to accelerate my C language code running in PC. Therefore I transform partial C language code into FPGA code on SOCKIT board(http://www.altera.com/b/arrow-sockit.html)....
View ArticleBUG ? QSYS version 13.1 quartus
Hi I have a problem with QSYS in Quartus II Version 13.1 When i create my design in QSYS and then generate it. And then make my top file, and compile my design it gives my errors:12152. it refers my...
View ArticleOne shot pulse
Hi all, I am beginner in VHDL. I am doing tutorial for one shot pulse. But, I am little bit confuse. What does 'idle' meaning in this code? and how do I can modify this VHDL code to generate pulse...
View ArticleIn ALTERA Monitor it works, in Eclipse EDS it doesn't?
Hello people! I have followed the tutorial "Introduction to Qsys" from the ALTERA University program where a very small VHDL system is created plus an instantiation of the Nios II and some switches as...
View ArticleClik here to view.
QSYS - NIOSII - JTAG_DEBUG_MODULE using a lot of logic cells
Hi, I'm using QuartusII 13.0sp1. In my Qsys design I'm using the Nios II/f version and the JTAGdebug module is set to Level 1. After compiling the QuartusII project, I can see from the Project...
View Article