library settings
When compiling Quartus II project, I keeps getting error: component ... not found or could not be instantiated. I have add my users' components library directory at "Tools->Options->libraries"...
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Neuron implementation in VHDL (code attached)
Hi all.I am just learning VHDL and as an exercise, I am trying to model a neuron in VHDL (attached the code). The neuron has three inputs, three weights and one threshold value (as entity inputs).The...
View ArticleThe limit of the ROZIPFS file system?
Hello, I use ROZIPFS successfully at several boards, but there maybe some limit, but what limit? 1. I find that if the ROZIPFS file size up to 2MB, the fopen() function usually can not return a valid...
View ArticleWaveform generation result window not getting
Hi, am using quartus II 13.0 version. During waveform generation, I am not getting the result waveform window. What will be the reason? new>university waveform vwf>node assignment> Run...
View ArticleI2c master/slave
Error: mtx_avalon_i2c: invalid command name "add_documentation_link" Error: mtx_avalon_i2c: One of top_level_hdl_module, a generation callback or instantiate_in_system_module = false should be set...
View ArticleIncreasing the speed of consecutive IOWR functions
Hi everyone, I have a dsp builder system and registers on it. When I want to write these register from NIOS by using IOWR function, there are about 30 clock cycles between two consecutive command....
View Articlestratix fpga user configuration fail
Hi, I am using stratix II fpga ep2s60f672c3n. while programming I am able to download .sof file to board. But user configuration not successful.it retains in factory configuration state. what may be...
View Articlehow to dump a .exe on a NIOS II processer
i have created a QSYS System which has a NIOS II processor standard and has a C code(DDR_test.c) which transfers data to the DDR3 UniPhy controller. !! Is there any way to directly put an .exe to the...
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problem VHDL help in code please
The figure 1 depicts the internal structure of the MAC circuit. This synchronous circuit is a Multiplier And Accumulator. The input and output ports of the circuit are described hereafter: ? The A and...
View ArticleHybrid Memory Cube HMC, IPs available ?
Hi, Stratix5, stratix 10, and arria 10 support HMC (Hybrid Memory Cube). Is there a HMC "bridge" planned to be added in a future version of the IP catalog ? Maybe this is still available, where i can...
View ArticleUsing DE0 Board And NIOSII To Connect SRF05 Sensor
I have purchased this DE0 board, a breadboard and a SRF05 sensor. I have basic knowledge of C and would like to create a sensor to detect the distance from an object in cm, I would like to do that...
View ArticleAltera DE0-nano. Struggling to make a SPI slave device
Hi. I'm new to VHDL and I thought I could try to make a slave SPI device as training, but it's not working quite as expected. Below my current code. It's compiles and upload just fine, but it's not...
View ArticleCan't fit design in device after upgrade from 13.0SP1 to 13.1
Hi, I have a projecto for the MAX V "5M240ZM100C5" CPLD, almost at the max capacity of the device. Previously I was using 32bit PC, Windows 7 and Quartus II 13.0 SP1 Web Edition, and was able to...
View ArticleDC signal measurement
Hi, What is a good AD/DA board that can be interfaced to a DE4 board and can be used for DC signals ? I've looked at the TerasIC daughter cards and they do not support DC signalling.
View ArticleDS-5 debug configuration
I installed Quartus 13.1.0.162 without problem. In C:\altera\13.1\embedded\ds-5_installer, I ran the installer.. also without problem. However, when I go into run -> debug configurations... and...
View ArticleLow Performance NPU with TCP/IP Stack using NIOS with Internal Memory only
Is there any application notes on implementing a low performance Network Processor Unit using the NIOS processor with only internal memory available in a Cyclone IV, EP4CGX15. There would be a need t...
View ArticleTiming measurement
Hi, Please i try to measure timing of block on the Nios through alt_timestampe() function. It work fine :), but my probleme why when i measure a block that's contain for example 10 instruction (10...
View ArticleGenerate Shapes using Verilog
Is its possible to display shapes (specifically a square or a rectangle) on a LCD monitor connected through a FPGA board by using Verilog HDL?? Are there references or sample source codes for me to...
View ArticleEVB for high-speed LVDS-to-LVCMOS conversion?
Does Altera have an EVB (or a set of EVBs) I can use for high-speed multi-input LVDS-to-LVCMOS conversion? I think what I want is a converter that is an LVDS bus on the input side to parallel LVCMOS on...
View ArticleHow to transfer data from pc to sdram?
Hi, What program can I use to transfer data from my PC to the SDRAM or FLASH memory on the board? I am using DE0. For example I want to transfer the bit stream encoding an image file onto the SDRAM for...
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