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How to use HSMC (JP8) on DE2_115 ALtera Cyclone-IV Board
Dear Friend, I have altera DE2_115 Board and i am trying use pin on port JP8 (HSMC). each time i assign pin to this port and compile it generate an error. my pin name is P_DATA and i am trying to...
View ArticleHelp programming CPLD with graphic editor
Hi to all I'm starting using CPLD with MAX plus II and Quartus graphic editor. I know It's not the best way but It's the easyiest for starting. No problems with logics, inputs and outputs. Now I like...
View ArticleUsing CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?
Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Requirement is Rx...
View ArticleUSB Blaster obselete?
I recently got a notification from a distributor that the USB Blaster (PL-USB-BLASTER-RCN) is being discontinued. I haven't been able to find any documentation on Altera's site to confirm this, but I...
View Articleprocess flow for generating NIOS + TSE
Hi, I need to generate an TSE solution to Cyclone IV GX, where the datapath is: Memory (internal in the beginning, DDR2 later) => SGDMA => TSE => PCS => PMA (GX tranceiver) => SFP module...
View Articleproblem in signaltap
Hello friends, I'm a newbe in signaltap tool in Quartus II. I can configure the signaltap to see input/output pins changes. But when I want to see the changes of registers of my design, it just shows...
View ArticleVideostrem synchronisation
Hello, I have a Altera Cyclone III Development Board and try to synchronize some Videostreams. They are delayed horizontal and vertical. Is it possible to synchronize them onboard without using...
View ArticleHow to do large scale verification
I am almost done my CPU project which involves a 5 stage RISC pipeline with exceptions and all of that lovely stuff that you will find on a modern low-end processor (no caches or virtual memory). I am...
View ArticleHard EMIF QSYS generation problem
Hi all, I'm running Quartus 12.1 on Win 7. I'm trying to migrate my design from "SOPC Builder for Cyclone 4" to "QSYS for Cyclone 5". Because the Altmemphy is no longer suported, I created a UniPhy....
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2-decade up/down BCD counter ,, need help
Hi all.. i need some help in my project, i have attached the PDF file. so please if anyone can help.. Thank u ;) Attached Files project_hdl.pdf (25.3 KB)
View ArticleCyclone III configuration with EPCS4 issues
Hi all, I need your help concerning an issue of serial flash configuration . I have cyclone III FPGA (EPC3C16) connected on a board with the serial flash EPCS4. I have only one header(JTAG) , so in...
View Articleconversion of matlab code to C language program to run in nios2..how.?
Hii, i have hdl coder in matlab v2011. when a matlab file is converted into C language file then its giving errors. what is the procedure to generate C program successfully in nios after converting...
View ArticleWhat's the syntax that defines the path of a generated entity in Quartus .qsf...
Hi, In a .qsf file, I'm trying to set TERMINATION_CONTROL_BLOCK via set_instance_assignment -name TERMINATION_CONTROL_BLOCK "e1:i1|e2:i2|e3:i3|s" -to o_pin[0] -tag __p0 This approach works as long as...
View ArticleQuartus II 9.1 SignalProbe Compilation
Hi, I am working on a script file to support SignalProbe compilation. The operation sequence is: check_time echo -e "$CUR_TIME: Compilation flow starts..." quartus_sh --flow compile $PROJ_NAME >...
View Articlecyclone5 E vertical migration doesn't work
I'm converting a design from cylone 3 to cyclone 5 and I wanted to set migration devices to every 5CEFAxF23I7 part available, but the compatible migration devices list doesn't allow choosing all...
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How to do the timing constraint?
Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA?...
View Article[Help] half band filter in verilog
I am trying to write verilog code for half band filter coef 19, and stimulation using modelsim, I am beginner in verilog coding, can anyone give me some example-code about this , thanks :((
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Clocked Video Output maximum Image width
Hi All, I'm currently working with the Clocked Video Output Altera IP, everything works for me for the moment. Now, I would like to Output a stream with an Image width of more than 2600 pixels, but the...
View ArticleWriting to SRAM from VHDL and using NIOS
Dear All, For a schoolproject I am working on a spectrum analyzer. I have downloaded the Altera University program and I modified de C code so it will display a nice coordinate system. Outside NIOS I...
View ArticleData Logging from FPGA to PC
Hi !!! I am still a newbie to digital world. I wish to use the UART in SOPC to send some data to (RS485 interface) my laptop for logging purpose. Laptop does not have a RS485 terminal so i am planning...
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