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SPI Master Timing Constraints
I know there is a lot of discussion on this board regarding timing constraints, but I couldn't find this topic well addressed. I have a system where my FPGA interfaces to an ADC using a SPI like master...
View Articlehow to enlarge the input string width of lpm shift register?
Hello all, I'm trying to work a parallel input to serial output and might need up to 1000~20000 bits input string. But the megafunction I know from lpmshiftregister cannot support such long parallel...
View ArticleCan't suspend when debugging using EDS12.1
I'm using a design created in Quartus 11. It runs from flash. It containts a NIOS II core. In EDS 12.1, I get the problem that suspend (pause) doesn't work. Steps to reproduce: 1. compile a simple C...
View ArticleMechanical Drawing for Stratix V DSP Development kit?
Hi, Does anyone know where i could find the mechanical drawing for the Stratix V DSP Development kit? I've looked at the resources that Altera provide but i just can't find one. I'm only looking for it...
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How to synchronize a PLL with a clock signal
In my design I require there to be a 100 mhz clock signal and a 50 mhz clock signal. I have an 50 mhz clock source so I decided to use a PLL to convert it to a 100 mhz clock. The only issue I have is...
View Articlelpm functions with no clock
Hi I am very new to fpga so apologise if these are dumb questions but I have searched all over and cant find any help. We are trying to use some lpm functions concatenated together, a mult_accumulator...
View ArticleNios 2 can't locate the USB Cable
Hello, I made a testing system for my LCD with the SOPC builder. I was able to program and verify it as well in Eclipse. However when I started my PC today, I saw that the C program can not run, since...
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ModelSim Altera edition Bug?
I recently starting prototyping my hardware design using Modelsim Altera edition. I am struggling to figure out what is going wrong with some of my sequential hardware (Its an ALU). The ALU instruction...
View ArticleMatlab automatic exit, when I click on Compile
OS: Windows 7sp1 Ultimate(32bit) Altera Quartus II : 12.0sp2 (32bit) Altera DSP builder: 12.0sp2(32bit) Matlab: MATLAB R2012a Simulink simulation done right, double-click the Signal Compiler, click...
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Sending coefficients of degree 1000 from UART to custom logic with Nios II...
Hi, I'm pretty new to all this Nios II development and would like to ask advice on the best solution to my project. After receiving coefficients from an UART I have a 2000(GF3 coefficients) char...
View Articlede0 nano and lcd panels
Hello all! I have tried to figure this out on my own but have not been able to convince myself... is the de0 nano board, with its 50hz clock, capable of driving a lcd panel that has 7:1 lvds interface...
View ArticleArticle on Chinese proxy, missing contact !!
Dear all, I found this article on the Chinese version of Altera website Title : "Design of NIDS Pattern Matching System Based on SOPC" URL: http://www.altera.com.cn/education/u.../sep2011_3.pdf The...
View ArticleUART interrupt never occurs
Hi all, I am trying to use UART with interrupt on a NIOS II/e system but it seems like the interrupt never occurs. Before main(), I declare the pointer and the ISR: Code: alt_fd* fd="/dev/uart_0"; void...
View ArticleHow to identify if your design has a race condition.
I am currently working on a CPU and I managed to make it run an sequence of instructions (All it does is add 1 to a register and then store it into a memory mapped device which controls LEDs on my FPGA...
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How to connect on-chip FIFO in QSYS?
Hi all, I believe that my problem is very simple, but i'm new in QSYS and can't prepare a working design for FIFO. I have DB4CGX15 development board and building PCIe design. On current step i'm trying...
View ArticleDE2-115 Development and Education Board --- User guide
Hello, We are planning to work with DE2-115 Development and Education BoardSo, am looking for document or User guide of this board. Can any one help me out. Thanks raja.
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Reset Vector on Flash Memory
Hello, I'm new in Nios II and have two questions for you. I want to control my Clocked Video Input and Output via Nios II. First question: I begin my Nios II experience with this training video:...
View Articletiming requirement not met
Hello I'm kind of new in the world of FPGA and puzzled with a timing warning message sent by quartus. This fonction extract ratio info of an arbitrary PWM signal every period and send the ratio over a...
View ArticleCan Avalon-ST Dual Clock FIFO's fifo depth exceed 32?
accroding to the spec <ug_embedded_ip>P15-4,the descriptions for parameter 'FIFO depth',legal value is ONLY 1~32. But when I use Qsys ver 12.0 to add the DC_FIFO component,I can type in '1024' to...
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