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FPGA can't properly work at my input CLK.
In my design,I found the clock can not properly work. The input clock is 66Mhz, if this signal directly is connected to the output pin, the output will get a signal of 66MHz. That's ok. BUT!!!!!! If...
View ArticleUSB 2.0 Slave HwLib
Hello! I am developing an application for the Cyclone V where the board is connected to a Windows PC as a USB 2.0 slave. I have following wishes: Use case 1: The board collects data and provides it to...
View ArticleUpgrading Arm Linux Kernel from 3.7 to 3.13
Hello Friends, I have Altera SoCKit - The Development Kit http://www.terasic.com.tw/cgi-bin/pa...yNo=167&No=816 it shows that it has Linux Kernel 3.7.0 (by typing the command on PuTTy #uname -r)...
View ArticleNios II Gen2 core error
I just migrated my nios II to Nios II Gen2 core. I got a error as below. i tried to set instruction and data cache size to none. still give same error. /HAL/src/alt_remap_uncached.c:52: warning:...
View ArticleRHEL 7/ CentOs 7 support (kernel 3.x support)
Hello! Is it planning to support RHEL/CentOs 7 in Altera OpenCL SDK? As for now, the problem with compiling linux drivers for 3.x kernel.
View Articlefir filter for fsk demodulator
Hi, i've realized an i_q demodulator for fsk message. The frequencies for the 0 and for the 1 are spaced 400Hz; the baud rate is up 200baud. The frequencies are in the audio range (for example...
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My onw lights example is crashing
Hi. I created my own example project from a altera introduction pdf to use some buttons and leds. Thats the link to the tutorial ftp://ftp.altera.com/up/pub/Altera_M...PC_Builder.pdf. My board is the...
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Nallatech 385 OpenCL BSP - Update from 13.1 to 14.0
Hi, In order to update your board from 13.1 to 14.0 you will need to: Install the Altera Quartus-II 14.0 / Altera OpenCL SDK 14.0 ToolsSet up your environment variables to use Altera Tools 14.0...
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Problem simulating FSM
Hi, I am trying to simulate a FSM using vector simulator... the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation all signals...
View ArticleURGENT need help with implementing sha 256 on altera cyclone II
Hi i am a beginner . I need help with implementing sha 256 on altera cyclone II board so that i can use it as a testbed to study side channel analysis. I am looking for a fully working code , that can...
View ArticleURGENT need help with implementing sha 256 on altera cyclone II
Hi I am looking for someone to help me with implementing sha 256 on altera cyclone II board. thanks Liz
View ArticleIllegal constraints of channel pll to the region (0,13) to (0,33)
Hello all, I want to use channel 1 and channel 4 of cyclon v gx (6 - xcvrs fpga) for different protocols with seperate sets of clocks( for tx pll and channel cdr) for two channels.i.e. for channel 1, I...
View Articlelooping over a string character by character in Verilog
I'm attempting to send a string character by character over a serial port. I have the serial port down, but I don't quite see how to implement a changing index on a string... Ideally, my module would...
View ArticleAddress correspondence VHDL/C
Hi, I have a design with hardware writing 32-bit data in a 32-bit memory and software (written with Eclipse and running on a Nios II processor) reading it. I start reading from **_BASE address found in...
View ArticleCyclone IV nCONFIG pin is not stable
Hello everybody, I have a strange hardware problem and hope somebody can help me. I made two Cyclone IV testing boards. Both have the same problem: After power on, everything seems ok. The nCONFIG pin...
View ArticleAltera Cyclone V Development Kit Jumper Postion
Hi I have a really fundamental question regarding the Altera Cyclone V Development Kit that I just couldn't find anywhere on the net or in the documentation: For the jumpers and switches on the board,...
View ArticleNios II Gen2 - Tethered Design - Can't go back to untethered
Just a note to people thinking of trying the NIOS II Gen2 processor. We have a license for NIOS II but that doesn't license NIOS II Gen2, at least not the preview version anyway. Also after removing...
View ArticleBrand new Bittware S5-PCIe-HQ not working with Quartus 13.1 CentOS 6.5
Hi, We have started working with this FPGA on CentOS 6.5, we managed to get the board recognized by Linux and we can even use the Bittworks Toolkit to read sensors and communicate with the board. The...
View ArticleDDR3 "verify fail" when applying little modifications in Qsys
Hi , I have designed a NIOS II-e based system running on DDR3 memory and the system works fine but when I do small modifications in QSys (eg. add an interval timer) in some cases I face "verify failed"...
View ArticleQuartus II (Subscription Edition) does not list Stratix devices
I have just installed Quartus II (Subscription Edition with a license) V 13.1.0.(Build 162) on CentOS. Why am I unable to select Stratix V GX from the devices under Device Familly when I try to create...
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