Design using TSE ethernet mac megafunction : Modelsim simulation issues
Hello, I am using the Triple-Speed Ethernet MegaCore Function on my design. I've used the .cmp file generated to instanciate the core. When i want to simulate the design with modelsim (using my own...
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help with register to register timing constraint
Hello, I'm stuck on what is most likely a simple problem. I'm trying to constrain a signal in my design, but I'm not sure exactly how. I've tried a couple different ways and figured it would be better...
View ArticleArria V Transceiver Reconfiguration Registers
Hi, I am new to Altera but have been using Xilinx and to a lesser extent Lattice devices for years, so please forgive me it this is some well known issue I am not privy to yet... I have a design in a...
View ArticleProblem with credits for PCIE IP
Hi, I am working on a Stratix V PCIE Endpoint using the PCIE Hard IP and ran into a problem issuing packets. The block is configured to 128 byte payload, so that should be 8 data credits for a memory...
View ArticlePCIe Hard IP returning stale data for Cyclone IV
I have recently ported a PCIe endpoint design working on Arria V to Cyclone IV , ( Transciever Starter Kit ) . I need to go back but don't believe I see the problem on Arria V which is a very similar...
View ArticleALTERA QUARTUS II + Signal TAP + Change triggers without recomipling...
Hello guys! One question, Is there any possibility to change the trigger options in signal TAP without recompile the entire project? I don't want to do an incremental compilation or rapid compilation....
View ArticleEmbedded constraints
Hello. Using altera_attribute I am trying to place constraints in Verilog source. The exact line is: Code: (* altera_attribute = "-name SDC_STATEMENT \"create_clock -name clk143 -period 7.0 [get_ports...
View ArticleDE1-SoC + D5M
Hello, I have a small question about the compatibility of the Altera D5M camera module - hopefully, this is the right forum to ask such questions. I would like to implement the camera in my image...
View Articledivision procedure in schematic programming
i want divide an analog input say 4sinwt....so max value is 4. i want to divide the signal by 5 so output will be 0.8sinwt. so how i program through lpm_divide blockto get such result.
View ArticleGigabit Ethernet with GX FPGA
Hello all! Does anybody has experience in designing systems which include a GX FPGA connected to Gigabit Ethernet SFP modules? Is there a design guide how to do the layout, especially for the impedance...
View ArticleInstall Quartus II Web Edition 14.0 for Windows 7 32 bit
Hi I am trying to install Quartus II Web Edition 14.0 for Windows 32 bit but i unable to find in download page as it is downloading 64 bit software.. Does this version of software is having 32 bit...
View ArticleExcessive logic utilization from memmove
The following code is similar to a memmove() operation. This code results in a significant increase in logic utilization. The 'rep' member on the struct is defined as an unsigned char. Is there a...
View ArticleCan I use EPCQ32 with Cyclone III?
Hello, I mistakenly used an EPCS16 (8-pin SOIC) in my design with a Cyclone III EP3C120. Active serial has been working but if I use more than half the chip then my program will probably not fit in...
View ArticleReserved SignalProbe Pins
This has got to be a stupid question, but I just can't figure it out. So I've used the Pin Planner to reserve a few named pins as SignalProbe outputs. They're named TP20-TP23, after the labeled...
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Help!!
Im trying to build a clock but when I do it it goes in sequence from 0:58:00, 0:59:00, 7:00:00...It goes from 59 mins and 59 seconds to 7 hrs and then continues....it basically skips by 7 everytime. If...
View ArticleProblem porting the JBC Player in an Embedded System
I ported the JBC player (Jam STAPL ByteCode Player Version 2.2) for In System Programming per AN 122. When I attempt to read the ID code using the READ_IDCODE action, I get the following error Device...
View ArticleHelp! GCC compiling error:arm-linux-gnueabihf-gcc:not found
I'm doing gcc compiling on ubuntu according to the tutorial:my_first_hps. Code: jungu@ubuntu:~/altera/14.0/embedded/my_first_hps$ arm-linux-gnueabihf-gcc...
View ArticleSGDMA Memory to Stream Problem
Hi! I am working on SGDMA in MM -> ST configuration. My main aim is to read a frame from DDR2 SDRAM and send it via streaming interface to my next custom made IP. In order to understand and grip the...
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NIos2 boot from EPCS
Hi I am trying to boot nios2 from epcs 16. iam using the quartus13.0sp1. my code just to blink the leds when nios ios running .i have follwed the the steps of the document which i have attached with...
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Timing constraints for DDR ADC Interface with AD9643
Hi, I am working on the DDR Interface with the AD9643 ADC from Analog Devices, but I am not able to catch proper signals! May be someone is familiar with 200MHz DDR Interface, here some informations...
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