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Functions, Procedures, Packages, TextIO, and Sign Magnitude Math
Hello, I need to create a package containing 3 functions and a procedure that will compute the addition, subtraction, multiplication, and division of two signed magnitude binary numbers respectfully....
View ArticleTTK .. having difficulties
http://www.alterawiki.com/wiki/Use_T...gnal_Integrity Using this reference design ... I tried with Quartus 13.1 and 14.0 and in both cases after loading the .sof and starting the TTK , the GUI comes up...
View ArticleCLK pin voltage on Cyclone IV devices
Specifically referring to the EP4CE6 devices, which have a core voltage of 1.2V, what logic level should the CLK input pins be at? Do they reference the core 1.2V level or the VCCIO level of the bank...
View Articletrouble generating system and compiling with SOPC builder
Hi, I have been trying to follow the online training for SOPC builder to get the system generated and compiling. I am using the 30 day evaluation license of quartus II (10.0). I created a project...
View ArticleEthernetBlaster II weird operation
I opened an EthernetBlaster II two days ago. Brand new out of the box. Attempted to login using the host name, but eventually had to use the 192.168.0.50 address, when the DHCP didn't appear to work....
View ArticleAcheiving 480Mbps on Max10 A7 FPGA(FPGA Beginner)
Hi, In my new design i have selected Max10 A7 FPGA. i have a specific constraint for a particular signal. the signal have 480Mbps data rate and it should be connected to LVCMOS 1.2V IO. Is it possible...
View ArticleUsing Altera GPIO Lite Ip core as bidirectional DDR
Hi, I have a signal whose data rate is 480Mbps. it is a DDR signal. I would like to know whether by using GPIO Ip i can acheive this ?. What would be the IO standard for the ddr output of GPIO IP ? Can...
View Articlesimple graphics gui
Hello: I am just getting started with the MAX10 FPGA. I would like to add some simple gui graphics capability, using a small 4 inch color "dumb" touch lcd to display messages & pushbuttons. (NO...
View ArticleUnderstanding how loop unroll works
Hi everyone, I just want to make sure that I understand how loop unroll works correctly. 1. I always thought of loop unroll as SIMD for loops. Is loop unrolling enabling concurrent execution of...
View ArticleError while simulating nios ii with custom component
Hello all, i want to simulate a Qsys system which contains nios ii and a custom peripheral. I created the testbench system in Verilog (Simple, BFMs for clocks and resets) and launch modelsim through...
View ArticleHow to properly constrain SPI - like interface if SCLK freq = FPGA main clk freq
Hi all! My problem looks like wdshen'sproblem in that post: http://www.alteraforum.com/forum/arc...p/t-32549.html. But it has some interesting details. My ADC mode is here -...
View ArticleAdding Lib in Model Sim
Hello, I am using sfixed data type in my vhdl code. (using ieee_proposed) When I try to compile the code in model sim, it gives me an error. Library ieee_proposed not found. Can anyone tell me how to...
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can not export the master interface of avalon-mm pipeline bridge
I need to make Qsys export an Avalon-MM Master for configuring a IP core which has a Avalon-MM Slave interface, but I got this error from eclipse while downloading the software: No Nios II target...
View Article"Enable internal scrubbing" option unavailable in Quartus II 15.0.0
In QII v15.0.0, I cannot enable internal scrubbing in "Device and Pin Options" dialog. Anyone know what's going on? The design is for Arria V (5ASTFD5K3F40I3 -- on Arria SoC dev board).
View ArticleCan't finish creating NiosII project
Hi Everyone. I would be grateful if someone could help me with this one: I have followed this video tutorial step by step: https://www.youtube.com/watch?v=1a_cD6FBROA I have made the same exact...
View ArticleDE2-115 and Terasic High Speed AD/DA daughter card
Hi everyone, I am going to use the terasIC High Speed AD/DA daughter card (http://www.terasic.com.tw/cgi-bin/pa...English&No=278) in combination with the DE2-115 board. Unfortunately i have no idea...
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Unable to install any versions of Quartus II Web Edition
Hello Altera forums, I've continuously tried to download different version of the QII Web Edition such as 13.0 and 15.0. Currently I'm attempting to install the full-featured ISO of Quartus II 15.0,...
View ArticleFir ii ip
Hi, I designed a low pass fir polyphase interpolator filter with matlab. Now I have the coefficient but I am not sure about what settings I have to use with fir compiler to make the filter. Is right to...
View ArticleDDR3_CONTROLLER problem
Hi, There is an error when I complie the DDR3 controller simulation design： Error (17044): Illegal connection found on I/O input buffer primitive DDR3_example_sim_e0:e0|DDR3_example_sim_e0_if0:if0...
View ArticleDirect B-LVDS and Hot-Swap in CycloneIV
Hi guys! I dont know how to contact altera directly so iam asking for help you. Iam working on project where i will use CycloneIV on hot swappable cards. BLVDS and diff clock inputs will be connected...
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