64 bit Avalon MM to ST FIFO for PCIe 3.0 IP core
Hello everyone I am working on integrating the PCIe3.0 IP core from Altera with my existing application. So far we have been using SFP interface to communicate with the host and we would like to use...
View ArticleVIC/NIOS misses interrupts
Hello all, I have a QSys made SoC consisting of a NIOS II/f, which is connected to several peripherals including an Altera VIC, which accepts 3 different interrupts. I think the Avalon Bus...
View ArticleExternal interrupt not triggering software exception
I currently hav a push button connected up to my IRQ input on my Nios. When the button is asserted, I expect to see my program counter jump to my exceptions section in my assembly source code. When the...
View ArticleRunning a simulation in Modelsim
Hi, Appreciate your help regarding running simulations in Modelsim. I have a set of modelsim files that runs on modelsim altera starter edition version 10.0c. I have check and it works. It doesn't run...
View Articlework flow creating IP component from vhdl in Qsys
Hi i experience some confusing behavior when i work with Qsys and Quartus to create/modify vhdl files used in IP components used in qsys. Here is what i do.. 1) edit vhdl file used in Component...
View ArticlearriaII GX power sequence
Is there one every a rule of the power supply sequence in ArriaIIGX? In altera eva. board,VCCA,VCCA_PLL(2.5V) are turned on after VCC,VCC_PLL(0.9V). PGOOD of VCC,VCC_PLL power supply is connected to EN...
View ArticleSubprograms for bus functional model
Hi, I have a problem that is driving me crazy! I hope someone can help me. I am trying to make a bus functional model for simulation and using VHDL 2008 is fine. The subprogram interface should look...
View ArticleChannel problem
Hi There are two kernel functions to communicate with each other by using channels. __kernel void producer(...) { // N threads int sum = get_global_id(0); write_channel_altera(ch , sum); } __kernel...
View ArticleEMULATOR issue can't find vs linker LINK.EXE
when i run the following command aoc -march=emulator device/boardtest.cl I get Error: aoc: can't find visualstudio linker LINK.EXE. Either use Visual Studio X64 Command Prompt or run...
View ArticleNode instance "tcm_address_w_check" instantiates undefined entity
Hello. I am using Quartus 13.1 and Qsys. I can build my project using verilog, qsys and NIOS previously. But I added the clock component at pll in qsys. I had error at build of quartus (using verilog):...
View ArticleAccurate Powerplay Analyser results using Uniphy
I am trying to figure out some solution of getting accurate results (well at least ones that Quartus's metrics say are good) from the powerplay tool when using a uniphy block. From my understanding the...
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SDC file + Quartus II Text Editor issue
Hi guys, I think that there is an issue with the text editor of Altera when I try to modify the SDC files. This text editor should be confgured to generate linux output in order to have LF instead of...
View ArticleChannel board I/O
Hi, I would use the I / O card, DE1SoC. By following the guide provided by altera, I realized that I have to use interfaces/channel that are in the file "board_spec.xml". However, in this file there...
View ArticleOdd clBuildProgram function error
Hi everyone, I am actually working on implementing an existing GPU OpenCL benchmark on an FPGA. Recently I am stucked on a really strange problem: I am trying to run the simulation of one of the kernel...
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Unable to simulate ALTSQRT in ModelSim Altera
I wrote a small program to try out the altera sqrt ip. i included the module in a quick script i wrote, but when i try to simulate it, i get X values in some of the bit fields. I thought it might be a...
View ArticleTSE Ethernet RGMII for NiosII running Linux
I have been trying to get a SoC that would run Linux for the NiosII. Then I want it to support Ethernet. I have been using TSE so far, but no success. Does anyone has some ideas about how I could have...
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Gated transceiver operation on Transceiver SI Development Kit Stratix V GX board
Hi, I have been trying to use the transceivers on the Transceiver SI Development Kit Stratix V GX board and managed to successfully use them in continuous mode. However I would like to be able to make...
View Article#pipeline stages after using aoc to generate the report ?
Hi , Is there any report showing how many pipeline stages / stall clocks (using NDRrange - Multi-threads) by using aoc command ? Thanks.
View Articlesoc_system_board_info.xml/hps_common_board_info.xml common accross most...
I'm using De0-nano-soc & De1-soc from Terasic .. neither has soc_system_board_info.xml & hps_common_board_info.xml included in the packages that arrived & Terasic is claiming their linux...
View ArticleMultiple kernels in a single OpenCL file
I'm concerned about area usage if multiple kernels are used. If I understand correctly, if an OpenCL source file contains multiple kernel functions, all of the kernels will be instantiated...
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