Can I use the Nios II Eclipse S/W Debugger if I don't have the quartus project?
I have working Nios S/W and a .elf file (and my source code). And I have a working FPGA. The H/W designers developed the FPGA under Linux, in a completely different environment. I wrote my Nios S/W...
View Articlehow to save and use image in memory
Hi, I have an image processing application, I don't know haw to save the image in memory, can any one help me how?? can I use an .txt file and read it with vhdl code, or there is an other method. thank...
View ArticleSignaltap modify actual circuit when triggered problem.
Has anyone seen a issue where, when the "Run analysis" on Signaltap is clicked, the operation of the actual design actually changed? I am using signaltap to monitor a ADPLL loop control. I have some of...
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BSP failure in Altera Monitor Program (AMP)
Dear all, very good day, I've problem with Altera Monitor Program (AMP), it mentions a failure in updating the settings bsp file. I firstly create the bsp file on commands line, and then this problem...
View Articlepcie communication with fpga
Hi I am using cyclone 4 our own custom board which is working fine with 32 bit computer system using jungo driver but i dont have the jungo driver for 64-bit system so how can i test the pcie board...
View ArticleSOPC warning- Quartus 12.0-
In my sopc builder I don't use any custom component. But it shows the following error msg. cpu_0:Custom Instruction components can be edited through the component editor Is this a problem? In nios ii...
View Articleselecting parameter based on reg value - verilog
Hi , I have a set of parameters ( constants ) . I want to select one parameter at a time based on a register value (ex. reg [3:0] sel_value ) . Or i need to conditionally instantiate a module . ex . if...
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My clock port cannot be matched as a port
I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis". Now...
View Article[Help] Use Jam STAPL Player to Update CPLD on Linux, but cannot update twice.
I want to update my CPLD program through the Jtag, which is just simulated with four pins of CPU. I write a linux driver to control the CPU pins, port the Jam STAPL Player to linux and compiled it as...
View ArticleWhy PCIe signals tx_st and rx_st are different for CIV and CV in QSys?
Why does "Cyclone V Hard IP for PCI Express" have tx_st and rx_st as Avalon-ST sink and Avalon-ST source in QSys, but "IP Compiler for PCI Express" for Cyclone IV have it only as Conduits?
View ArticleHow much violation is ok?
Hi, I am working with a design on Stratix II Speed grade 3. I am consistently getting slow model clock setup violations of around 150 ps. Is it ok to waive these violations? My design is for a...
View ArticleUndefineable NIOS reboot @ RS232 communication
Hi all! I have a problem with my NIOS II application (Cyclon III) which communictes with a host application over RS232, and hope to get some advices, maybe solutions, here! :-) Problem Description: 1....
View ArticleIs it possible to select multiple memory regions for global variables?
Is it possible to select a memory region for specific global (RW or RO) variables? This would be different from the usual region for the RW/RO data. Effectively I need the loader to copy from the image...
View ArticleFast ethernet without mac/protocol
I have a network that is already working and I want ro take this data without filtering, I want to connect my de2-115 board with the phy connectors and only sniff the data. I the same way I have my...
View ArticleNew to VHDL. . . and this error is adding years to my life!
Hello all. New to this forum, and will probably be more active since this stuff is not innate to me. Anyways, I am trying to make a stopwatch that has the following properties: 1. When you press KEY3,...
View ArticleNEED Fit or MTBF Numbers for Part #5SGXEA3H1F35CZN
Hello. I'm needing to find the FIT or MTBF numbers for part # 5SGXEA3H1F35CZN
View ArticleHow to use the Altera Monitor program with Qsys generated NIOS system
Gentlemen, I have generated a simple custom Qsys NIOS processor. It generated with just a couple of warnings. I then instantiated it into a Quartus project and it compiled fine. I next went to test it...
View ArticleISP 1761 VHDL USB Peripheral Controller Timing Issues
Hi Altera Forum Members, I am currently Designing on the Terasic DE4 with a Stratix IV EP4SGX230 and Quartus 12.1SP1(formerly just 12.1) for my Master Thesis. I have no experience with the Nios II and...
View ArticleHelp getting Quartus II 12.1 to work
I have an issue with Quartus 12.1. I downloaded the Altera installer to download and install Quartus II web edition (free) 12.1 and ModelSim from the top of the main download index on the Altera...
View Articlecompilation time
hi , i changed my previous project code with small changes. previous it was taking 5 minutes to full compilation , but now it is taking 25 minutes for full compilation(fitter is taking so much time) on...
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