SPI interface in Qsys
Hello, I want to learn if putting SPI core is the only thing we should do to interface two components with SPI and also if possible can someone help me with the connections. I plan that one side of the...
View ArticleFP Custom Instructions - exp() won't get any faster
Hi everybody. I'm working on a design using Nios II/f that heavily relies on floating point math. In Qsys I addedd Floating Point Hardware and I connected it to the Custom Instruction Master of the...
View ArticleRS232C Packet Loss
Hello, I am working with my custom board, and having problem communicating via RS232C. In very rare occasion, commands seems to be ignored, lost, or thrown away. My C code is somewhat like below:===int...
View Articlesimple VHDL program --> need help please
i have an external asynchronious signal (called "sig") which i have to count its rising or falling edges. i wrote a program which somehow ends very quickly --> after 2 rising edges, req_dist = 32...
View Articletimes() always returns 1 in NIOS II
Hi, I am trying to measure the process execution time using the following code... Code: #include <stdlib.h> #include "sys/alt_stdio.h" #include <sys/alt_alarm.h> #include "sys/times.h"...
View Articlecameralink with transceiver pins
Hi all, I would like to know if it's possible to acquire a Cameralink protocol with the transceiver pins. Indeed, cameralink is a 4 channel LVDS with a 7 serialiasation factor whereas transceiver...
View Articlecant make vsim +notimingchecks work
i enter vsim +notimingchecks one.vo into modelsim command line and it just opens one.vo file. when i simulate it; it still simulates timing delays. what am i doing wrong??
View ArticleXML file for GigE Vision camera
Hello, I hope somebody on Altera's Forum is designing GigE Vision cameras. As I know these cameras need XML file for configuration. Is there any fast and comfortable way to create this XML file?...
View ArticlePCIe Root Port Configuration using NIOS via Avalon-MM Interface on Cyclone 5...
Does anyone have refence code or steps needed for configuring PCIe (PCI Express) as Root Port (Root Complex) via the NIOS-II processor on a Cyclone 5 board using the Avalon-MM interface ? I'm trying to...
View ArticleEclipse compiling to wrong RAM space
Hi All, Having built a NIOS system with 32kB internal RAM and 32MB external SDRAM there seems to be an issue with the binary created by Eclipse / GCC loading into the wrong space. Initially the...
View ArticleCyclone 3 + EPCS controller (altasmi_parallel) + Alt Remote...
I would like to share my experience in implementing the remote update functionality in Cyclone 3 using EPCS controller(altasmi_parallel) and Alt Remote Update(altremote_update) Mega Functions. I would...
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How to constrain a DDR input with its clock on a general IO pin?
I am working with a design that involves a high speed ADC with my FPGA (a cyclone 4). The ADC samples data at 250MHz and puts its output on a LVDS bus 14 bits wide directly to the FPGA (the clock pin...
View ArticleDecimation or re-sampling filter
For a software defined radio, we need to resample down factor 1000x. Specifically, we are bringing in a signal at 20 MSps and then decimating down in real-time to 20 KSps [for processing gain]. How do...
View ArticleNios C-Code Size
Sorry if I am being a bit thick here. Been programming VHDL forever but C is still a little bit of a mystery to me. Can someone please tell me if there is a quick and easy way of working out how big my...
View ArticlePHY Control - access
Hello!! I'm very new in this fpga word and I'm trying to learn more about this world. I'm with a project that I'm getting 16 bit data already packet and ready to send, I don't have to implement the mac...
View ArticleVerilog to VHDL
Hi everyone, I am having a problem converting a verilog code to vhdl. I know there is a tool does that but it is not working properly. I did write the code in vhdl and the schematic is same. however...
View ArticleCan't view attachments to my service request in mySupport
I have a service request 10932055 to which I have attached files and the service request person (John) has also attached a file. When I try to view any of these I get an Altera page that says "server...
View ArticleThe project or revision name contains one or more of the following illegal...
Hello, I'm hoping someone can help me with this. I'm getting the following error when I go to open a project from my second hard drive. The project or revision name contains one or more of the...
View Articlede2 board expansion header
hi, i want to connect my ultrasonic sensor to de2 board and the sensor operating voltage is between 2.5 to 5.5V. Can i just connect the sensor using de2 board expansion header to power the sensor and...
View ArticleWhy do .SOF files sometimes get made instead of .POF? How can I force a .POF?
I am still learning Quartus II 12 and I'm building simple designs, like 4 inputs that get and-ed and or-ed and then output on Cyclone II devices. Most of the time Quartus makes a .pof, but sometimes it...
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