ModelSim ALTSYNCRAM Issues
Hi there, I use the altera 2-port RAM megefunction in my design holding 4 x 8bits. I have seperate read and write clocks, where the read clock is clocked on negedge and the write is on posedge. When I...
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How to define clock while using flip flop
I am new to VHDL and i am facing one problem while writing a code. In my circuit i have different components like half adder, and gate and flip flop. When i perform the check syntax, i receive an error...
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switch or elsif problems
Hi everybody, I am currently using Quartus II 9.0sp2 Web Edition, i'm trying to make a program to add some bits depending of this "switch" MFG_B12A1P_sml.jpg. i have 2 seven segments and 10 of this...
View ArticleWhat is saved in Quartus 7.2 (WebEd) "Project Save"?
Hello, Newbie here! OS: WinXP Pro Quartus 7.2 (WebEd) What is saved to disc via: File >> Save Project<klq> Is there a strategy available for saving just the IDE environment settings? Items...
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What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?
When I do simulation in Modelsim, in sim tab, there are "Assertion misses" and "Assertion hits", I attached a screenshot to show it, what is the mean of this? Thanks in advance. Attached Images 1.jpg...
View ArticleSynopsys VCS gets stuck
Hello, I am facing some weird problem with VCS. I am trying to simulate a simple RTL model with testbench in VCS. It's not possible include all the details of RTL model as its kinda big but in general...
View ArticleVIP Deinterlacer jumping
Hi all I use a motion adaptive deinterlacer with triple frame buffer In my design. When using frame rate, the output looks fine and stable for A few seconds but then the picture start jumping up and...
View ArticleHow to enable the nios 2 IDE?
Hello, I've used the Nios 2 IDE before but now I've installed a new Quartus II Web Edition and the Nios 2 IDE is not available, instead when I start the "Nios 2 build tools for eclipse" from Quartus...
View ArticleAltera Virtual Target
Hello, I am trying to setup the virtual target for the Cortex A9 with Trace32. When I type this command: sys.config listcore It should list the cores, all I get is...
View ArticleQsys port order in the symbol file (.bsf) ... random? How to fix? (v.12.1SP1)
Hi, I had to transform an SOPC bilder System created in Quartus 9.1 to a Qsys System in Quartus 12.1SP1 ... But now I'm running into a very frustrating issue with qsys ... I hope I'm missing some...
View ArticlePCIe Simulation : PCIe Root Port BFM transactions
Hello, I want simulate, with Modelsim, an Altera PCIe Endpoint design Qsys-Avalon-MM based. I begin starting with the PCIe Qsys example in Chapter 17 of the "IP Compiler for PCI Express User Guide"....
View ArticleMultiple Qsys files
Is it possible to use two different Qsys modules in a system simultaneously? I have a video system as my main Qsys block and I wanted to attach a dummy video source as a separate Qsys module. (It's...
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TSE (Ethernet) - Core does not transmit data on RGMII TX, rest works...
Hi all, I am facing a problem that I don't fully understand. I have an instantiation of the TSE core that I integrated into my application. In simulation everything (Receiving and Sending) works...
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the Altera FFT IP function well?
The following is IP Config 1.jpg2.jpg3.jpg When I force the DC to the sink_real,and sink_imag to 0 ;The FFT IP work as following;who can tell me why and how to solve. NP~TTO@N4}Z@H][LATLA{%J.jpg...
View ArticleInternal Error: Sub-system: VRFX, File:...
sir i've installed 30 day trial version of quartus 12.1sp1 recently and while compiling my design (using stratix), i am facing an internal error : Internal Error: Sub-system: VRFX, File:...
View ArticleNIOS IDE build differences
Hello all, I'm trying to locate a source to figure out the differences between NIOS IDE builds 63 and 93. I know that these are old tools but I'm stuck with Quartus 6.0 and NIOS IDE 6.0. I'm trying to...
View ArticleSeemingly easy Build question
I have a prebuilt full set of source files to write to an FPGA with an NIOS II OS to drop in. This set was built on a different system with a different license. Ideally, I would like to program the...
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Quartus II Web Edition 12.1sp1 Licensing (Asking for a license file)
Hi All I'm facing a little problem when trying to get Quartus II 12.1sp1 WebEd. When I run it, it is asking for a license! Visiting the page of Quartus II download ( Home > Design Tools &...
View Articlezero time loop in state machine
Hello, while working with a design, I am facing zero time loop in VCS. One of my state machine is causing this zero delay loop and after spending some time, looks like the following snippet of code are...
View ArticleTransceiver toolkits example modification
Hello I want to modify (sv_1ch_40b_10312mbps) trasciever toolkits example so that send GOLD codes sequence instead to PRBS . I will use GOLD codes sequence to encode random data at transmiter side and...
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