Always block within always block
Hi guys, Is it possible to use always@block within always block? The reason I want to do that is I try to construct multiple synchronised blocks using For loop, and you need to put loop statement in a...
View ArticleOn-Chip termination in Cyclone IV FPGA to interface it with the SDRAM
Hi All, I am dealing with the pin assignments specifications for Altera's Cyclone IV FPGA. I am using Altera's Quartus II software and using its QSYS tool I have designed a system to interface DDR2...
View Articlehelp from transceiver expert
Hi, I will be back to travel on new project using Altera startix V. It is my first work on this area and i need your help. I try to implement the design example for Startix V GX on wikialtera for...
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Timequest and ripple clocks ... how to set up?
I have a set of ripple clocks. Yes, I know, don't do that, but we seem to get a decent power savings vs enables. Now, I hope I'm not insane. I have a main global clock at 320MHz coming off the PLL, and...
View ArticleModelSim Altera bug in Create Pattern Wizard
I'm trying to use the pattern wizard on modelsim to simulate a simple flip-flop d that i wrote in verilog, i'm following the tutorial on altera.com/literature/ug/ug_gs_msa_qii.pdf and when i click in...
View ArticleVHDL Model for MIPS Processor
Hey everyone. I was wondering if anyone would be able to help me out in making a VHDL Model for the MIPS Processor. The requirements for the VHDL code are listed below. I have spent hours trying to...
View ArticleSelect PLL in Arria V GT D3
Hi Friends, I read Arria V device handbook, CLK[0..3][p,n] are connected to FRACTIONALPLL_XO_Y27 and FRACTIONALPLL_XO_Y18. So, how do I know which CLK is connected to FRACTIONALPLL_XO_Y18 will has...
View ArticleWeb Server connection
Hi, when i access to the board via the ip address it sends me the index page which exists in the rozips file,my problem is that i want to put an image in the rozip file and then when i access to the...
View ArticleWeb Server connection
Hi, when i access to the board via the ip address it sends me the index page which exists in the rozips file,my problem is that i want to put an image in the rozip file and then when i access to the...
View ArticleSelect an architecture using waveform editor in quartus ii 9.1 sp2
Hi, I would like to know how can I choose an architecture from an entity where i have defined several architectures ,using the waveform editor. can anyone help me? Thanks Fixe
View ArticleQsys tri-state controller: 32-bit flash to 16-bit data
I have a 32-bit flash device that I want to access read-only with the generic tri-state controller. Instead of a processor, I'm creating a state machine in Verilog and making it a custom component in...
View ArticleSimple binary problem
Hello guys, I want to convert decimal from dec_buffer to a bin_buffer. Example: dec_buffer[1]=1; bin_buffer[1][12]={000000000001}; dec_buffer[2]=2; bin_buffer[2][12]={000000000010}; dec_buffer[3]=3;...
View Article[DE2-70] SD card controller without Nios
my assignment is: read a picture on SD card and show it on LCD screen without Nios II somebody helps me with the SD card controller in Verilog?
View Articlereference design with DDR3 DIMMs
Is there any reference design with DDR3 DIMMs? Preferably for Stratix V and RDIMMs, preferably 2 8GB RDIMMs per channel.
View ArticleQuestions about clock group in timing constrain
I have a question about clock group. Assume in a design, there are two clocks: clk1 and clk2. They are outputs of a PLL. There are no data paths between clk1 and clk2, that means no signals will be...
View ArticleTSE bug with ff_tx_mod = 3?
Hi, did anyone see a problem with the TSE ethernet core when ff_tx_mod = 3? I tested my design, it works fine for ff_tx_mod = 0, 1, 2 but not 3. tcpdump shows 1 or 2 bytes missing. I checked it on...
View ArticleIPS-embedded suite contains DDR2 Altmemphy?
Hello, I am a bit confused about the IP licensing. What is the difference between the DDR2 IP Core with / without ALTMEMPHY? Which one is included in the IPS suite? Thanks for your help.
View ArticlePackage data
Hello, I need some pad dimension of the package. I could not find it anywhere on Altera site. Can you help? STRATIX II EP2S180 1508 pin and CYCLONE III 484 pin EP3CLS200F484. What is the pad...
View ArticleGet data continuously from sensors
The output of my sensor is digital data (1-bit stream). Now, I want to get this 1-bit stream to NIOS system continuously. What components should I add to create the hardware in Qsys? I selected the...
View ArticleALT2GXB implementation in quaruts 12.1
Hi, I have a reference implementation in which ALT2GXB is used which was done in quartus 8 or 9. I was not able to synthesis or regenerate this implementation with Quartus 12.1. Can anyone help me out...
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