Max II to Max V upgrade
I want to solder in my PCB Max V 5M160ZT100C5 instead of Max II EPM240T100C5 but PIN1 is different. In MaxII pin 1 is an IO while in MaxV is a GND pin Can I leave pin 1 floating? Thank you
View Articleextracting FPGA context
Hello, I have a problem in my project, I try to extract a context from a FPGA in order to start the simulation with it. More precisely, I'm able to save the RAM data into a file and initialize the...
View ArticleQsys EPCS configuration issue
Hi guys, I'm new to FPGA programming and I've came across a quite challenging noob issue. I'm using an EP2C5 and I'd like to use the EPCS4 in my board to expand its memory. In Qsys I'm adding the EPCS...
View Articlemaximum frequency from command line?
Hi, I have a question regarding the maximum frequency of megafunctions. If I generate a megafunction with its synthesis netlist file from command line, is there any way to quickly determine its maximum...
View ArticleProblem running software on Cyclone 3 board.
Hi all, I'm currently developing software application to run on my nios processor using Nios2 SBT. I have designed my board to glow the LED's depending on the values it reads from the register. I'm...
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Cyclone V + Micron DDR3 + Uniphy + NiOS == always freezing
Dear All, I beg your support (and begging I meant serious :(), after three consecutive weeks of having burned engineering time, I decided surrendering with that Cyclone V Dev board and to post a thread...
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NIOS IDE 11.0 problem: No associated NIos II hardware launch configuration.
Hi. I found a problem in my nios ide 11.0 software( Windows 7 32bit professional, Quartus II 11.0 ). When i debuged my project as nios ii hardware , the Nios II console posted a warning as following...
View ArticleLogic Lock Regions - are they allowed to overspill?
Right, bit of a complicated story - Ill try and keep it short. I have a project where we need to run an overnight 12seed run to hopefully get a single good build (Stratix 4, 70% logic, 90% memory and...
View ArticleIP Verification Variable Classes
I'm working to simulate some qsys designs with BFMs. While looking over the latest IP verification documentation I noticed an assortment of datatypes as either arguments or returns that I haven't see...
View ArticleuClinux and VGA
Mainly the title says it all. I am wondering if is possible VGA output is possible when using uCLinux. I spend the most of day figuring out if it was so, but so far I only got a blank LCD monitor to...
View ArticleWindows OpenCL Driver Installation
For Windows users of Altera's OpenCL 13.0 SDK, the driver installation steps differ depending on which board you use. The Windows OpenCL SDK installer does not install the driver automatically. After...
View Articleerrno 11 and system.h not generated
I have specified the .ptf file for my design which also includes custom instruction. While building I get the following error. All the specified files in the error are present in the correct...
View ArticleIs it possible to build a NIOS2 in a Cyclone V E FPGA Development Kit?
Hi everyone, is it possible to synthesize a NIOS2 that uses the board resources in a Cyclone V E FPGA Development Kit ? If the answer is yes, where I could get an example with all the peripherals...
View ArticleJTAG problem with Cyclone IV kit
I am using the Cyclone IV GX Transceiver Starter Board and Quartus 12.1. The board test system runs correctly. As I am new to FPGA programming, I followed the Nios II Hardware Development tutorial....
View ArticleGet a PAL or NTSC video in and mirror it to the VGA output
Hello everyone! I have to deal with a project that means in recognising numbers in a NTSC or PAL format video coming from a simple ccd camera (through the on board peripheral on the DE2 board). The...
View Articlefsck too early - mmu vs. nonmmu boot sequence
Thanks in advance. In the old non-mmu versions I used the "rc" file to do an fsck and then mount the compact flash drive. NOW - the scsi and ata have not probed the device in time so - /dev/sda1 IS NOT...
View ArticleProgramming Altera CycloneV Active Serial x4 - Spansion FL256SAIF00 Problem
Hi, I'm trying to interface a Spansion FL256SAIF00 to a CycloneV FPGA using active serial x4 mode has anyone had success using a Spansion QSPI device for programming an Altera FPGA? A Micron 25Q256...
View ArticleQ2 OS & PC Requirements?
Howdy again, I read through the archives, but did not see an answer. What are the computer resource requirements for the Quartus II versions .GT. 7.2? OS version. How much memory? Processor type,...
View ArticleNIOS2 on a Cyclone V E FPGA Development Kit ?
is it possible to synthesize a NIOS2 that uses the board resources in a Cyclone V E FPGA Development Kit ? If the answer is yes, where I could get an example with all the peripherals already mapped in...
View ArticleA question about vector port declaration
I have a question about port declaration which confuses me: In VHDL, for ports or signals, we can define as: A : out std_logic_vector(0 to 15); signal B,C : std_logic_vector(7 downto 0); I personally...
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