Hi everyone,
I have been working with AVRs and C/C++ for quite a few years and everything looked pretty much straightforward as i used CodeVisionAVR and did not have to dig in the manual of every uC i worked with. Recently i started a project (
http://www.youtube.com/watch?v=73ygBq9Wq_M) with a STM32F4 discovery board aiming to build a DSO with high speed ADC 16bits (100-250Msps) and a few (tenths) megabytes of memory to store the captured values. As i finally concluded, after googling a lot and asking for help in chat rooms, the most obvious solution was to use an ADC, connect it to a FPGA, connect a RAM chip to the FPGA and optionally also connect a uC such as the STM32F4 to the FPGA or just use Nios II as uC (depending on the CPU power needs of the app). In order to get to know a little bit about FPGAs, i bought a DE0-nano which was perfect for my case as it carries an ADC, a Cyclone IV, 32Mbytes of SDRAM and some sensors, leds, buttons etc. I was able to play a little bit with the leds and buttons based on a Nios II configuration but that was pretty much all i did. So, as i am not experienced at all with FPGAs and don't have a clue about coding in Verilog / VHDL or even thinking in terms of parallel processing, i would like to ask for your suggestions as far as my project is concerned.
My thinking is that an ADC 16bit 250MSps connected to a FPGA and a DDR2 or 3 will do the trick. The thing is that i have no idea where to start from. I know that a FPGA does have a huge advantages package that includes interfacing different types of levels such as LVDS (ADC), TTL/CMOS (uC) and memory chips at the same time which is fantastic. However, even though i used the Quarus 13 software not for writing my own HDL but using the MegaWizard, i have no clue which IPs to use and how in order to interconnect the ADC, DDR mem and probably an ARM uC such as a STM32F4. As far as i know the speed of 250Msps plays a huge role of whether selecting a Cyclone FPGA or a faster one. There will also be issues with the timing of the memory while capturing at 250Msps and so on. As i read, simulation must be done before proceeding with anything but of course after writing the HDL that will bring all these parts together.
- The ADC will be dual at 16bits 250Msps. The output of the ADC will be LVDS parallel (not serial). That would propably be the important key when considering which FPGA to use. Which do you think suits this project?
- I was thinking about using a memory chip close to 64Mbytes so that i can always run the ADC at max rate and still be able to show on my LCD low frequency signals by compressing time axis as well as doing other things that only very expensive DSOs do. Is there a memory like that when it comes to DDR2/3?
- Will a Nios II CPU be able to process fast enough the data from the memory? Not the whole 64Mbytes. For example, the RMS value of a signal would require (assumption) 10K samples to be calculated with a decent accuracy. Would such a CPU be able to draw fast enough on a 800x480 16bit TFT LCD via DMA?
- What should i be reading right now? Verilog?
I know that specific answers require specific questions but the point where i am right now is anything but guess-safe.
Thanks for reading.
Any suggestions are welcome.
Manos