Using VGA with FPGA

December 7, 2013, 2:35 pm

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Hey guys,

I am relatively new to FPGAs. I'm trying to use my FPGA to output a VGA signal. At first, my screen kept entering power save mode, but I realized my timings were incorrect (vsync, hsync, etc). I needed a 25MHZ clock for 640x480 resolution but my board is only equipped with a 50MHZ clock. I created a PLL to generate a 25MHZ clock. Now, I am receiving the error "Auto adjust in progress". Any ideas as to how I can fix this problem?

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Local memory in one work group

December 8, 2013, 4:00 am

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Say we define two __local memory A[1024] and B[1024] in the kernel function and the data-flow is DDR--> A --> B -->DDR, my question is that do they combine their read/write ports to generate common local memory system or preserve the individual read/write ports? I am sure that the common local memory system will greatly degrade the performance, even worse when many __local variables are defined.

According to the kernel log: " .. kernel number of local memory banks : 1 1 1 1 1 1 1 ", Does it mean 7 banks exist in my design?

The memory utilization is much more than the __local memory defined in the OpenCL code, do the delay operations (with wider datapath, e.g. 32) require a lot of Block RAMs when the OpenCL code has relatively complex logic? BTY, I have roughly read the *.v generated by the AOC, and a lot of FIFO (with *.IMPL = "ram") are generated for delay operations. Does it mean we should avoid complex logic by generating multiple kernels?

Stratix V PCIE hardcore not detected in bios with Intel chipset C600

December 8, 2013, 6:31 am

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Hi all,

I'm using the PCIE hardcore in Stratix V with Quartus 12.1sp1dp7.
It works on a Linux PC with Intel C200 chipset family, but not with another Linux PC (the same OS, Centos 6.4) with Intel C600 chipset family.
I'm wandering if the Altera PCIE hardcore needs different settings for different chipset due to compatibility issue?

Thank you very much.

Simon

Error 10327 confusion

December 8, 2013, 8:20 am

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Hello.
I am trying to make a simple UP/DOWN counter and I am fairly new to VHDL. I keep getting the following error
"Error (10327): VHDL error at Counter.vhd(51): can't determine definition of operator ""+"" -- found 0 possible definitions"

My code is

Code:

---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity counter is
        generic
        (
        startnum : natural := 0;
        N : natural := 16
        );
        port
        (
                --Inputs
                EN                :        in std_logic;
                synchr        :        in std_logic;
                asyncr        :        in std_logic;
                dir        :        in        std_logic;                        --0 for count down 1 for count up.
                clk        : in std_logic;
                --Outputs
                Y        :        out natural range startnum to n-1
        );
end entity;
architecture counter_v1 of counter is
signal cntconst        :        integer;
begin
process (dir)                                --dir in sensitivity list as when this changes we want this process to run.
begin
if (dir = '0') then
        cntconst <= -1;                                --this will count down when added onto to the counter value
end if;
if (dir = '1') then
        cntconst <= 1;
end if;
end process;
process (EN, synchr, asyncr, clk)
variable notsurewhyitworkswiththis        :        integer range startnum to n-1;                        --I tried to just use y but for some reason it won't allow that.
begin
if (en = '0') then
else
        if (asyncr = '1') then
                notsurewhyitworkswiththis := 0;
        else
                if (clk = '1') then
                        if (synchr = '1') then
                                notsurewhyitworkswiththis := 0;
                        end if;
        end if;
end if;
if (cntconst < n-1) then
        if (dir = '1') then
                notsurewhyitworkswiththis := notsurewhyitworkswiththis + dir;
        end if;
end if;
if (cntconst > startnum) then
        if (dir = '0') then
                notsurewhyitworkswiththis := notsurewhyitworkswiththis + dir;
        end if;
end if;
end if;
y <= cntconst;
end process;
end counter_v1;

---

It is starting tio get a bit annoying now, I have tried loads of things I read online but to no avail.

Any help would be hugely appreciated.

Can Quartus autodetect top level module(s)?

December 8, 2013, 9:51 am

≫ Next: ALTPLL output directly to FPGA's pin

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I'm trying to run Quartus from the command line like this:

quartus_map my_project --source=model.v --family=MAXV

Unfortunately, it seems that the project name (my_project) must match the top level module from my source. Is there any way to run quartus from the command line where the top level module is auto-detected so it does not have to be explicitly specified?

Other synthesis flows, like Yosys, automatically detect the top level. For example, for this fsm design: http://www.edaplayground.com/s/4/496 Yosys log outputs:
Parsing Verilog input from `design.v' to AST representation.
Generating RTLIL representation for module `\fsm'.

ALTPLL output directly to FPGA's pin

December 8, 2013, 1:14 pm

≫ Next: adding ddr2 controller to sopc

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Hi,

I know this question has been asked in different forms many times now but I don't get what happens in my case since I seem to do everything right. I'm using the DE0 Development and Education Board equipped with a Cyclone III EP3C16. I have the 50 MHz clock input on G21 (optional function CLK4). I configured a PLL to output a 1 MHz clock on c0 output and connected c0 directly to pin AA3 (dedicated pin PLL1_CLKOUTp).

When I compile I get the well-known warning from the fitter:Warning (15064): PLL "clock_ccd:clock_ccd_inst|altpll:altpll_component| clock_ccd_altpll:auto_generated|pll1" output port clk[0] feeds output pin "GPIO0_CLKOUT[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

Can someone explain why? I seem to use the dedicated outputin pin for PLL, I use c0 so what is wrong?

Thank you,
Sebastian

adding ddr2 controller to sopc

December 8, 2013, 6:54 pm

≫ Next: Avalon MM Template - Interfacing to external memory for Nios to execute from

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sir i m goa university student currently my group is working on altera video development kit. We r trying to interface cmos camera to ep2c70672c6 dsp kit.
We r facing difficulties in sopc. We are not getting compatible vga and ddr2 controller in quartus 13 to our kit. So we r trying to add this from quartus 7.2.
please guide us how to add that in sopc library

Avalon MM Template - Interfacing to external memory for Nios to execute from

December 8, 2013, 8:59 pm

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I'm a bit confused on the several template variations, pipeline/burst etc.

For example, I see there's different templates for reading and writing, yet for the nios to execute from it (including placing the stack/heap in it), it has to do both. So, in order to connect the nios' instruction/data to it in qys, , I'm imagining a single component would have to be created/instantiated that has both pipwline read and simple write templates.. is this correct?

Or Is there perhaps a better way of doing this? Not to complicate matters, but the "external memory", is actually a fifo (implemented in logic), that's closely tied to an sdram ip... if that helps!

Thanks!

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vga controller

December 8, 2013, 9:07 pm

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it is possible to use vga of de2 board to dsp board. Please reply

have Altera designed the MIPI IP?if you have , How can I get it?

December 8, 2013, 10:54 pm

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I'm using FPGA as a host to support MIPI protocal,it is expected to interface to the CSI-2 Camera.It is too hard to design the interface myself,I think of using some IP core,but I can't find any ip like this online. how should i do?

minimum system clock required

December 9, 2013, 1:12 am

≫ Next: Why 1 times DMA transfer only support 256K byte in Qsys DDR3 reference design?

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Dears, I'm making a SPI interface in FPGA to interface with the SPI interface of a processor. The details as below:
• SPI of processor will always act as master. Slave for FPGA.
• SPI Clk: 25mhz
• SPI working mode: SCK polarity=0; Phase=1;
• SS Polarity: low effective
• Data format: 16bit addr + 16bit data; MSB of addr indicates read(1)/write(0) operation


I have finished VHDL code and test bench. (see attachment for source code, test bench and DO file for Modelsim )
RTL simulation has been done in Modelsim.
In the simulation,system clock in FPGA was set to 100mhz. After simulation, no error found.
Can I anounce that: this design can accept 25mhz SPI data if system clock is 100mhz?


Or i ask this question in another way. If SPI clock remainis 25mhz, whaht is the minimum system clock required? What is the criteria?

Attached Files

• source.zip (3.0 KB)
• simulation.zip (2.3 KB)

Why 1 times DMA transfer only support 256K byte in Qsys DDR3 reference design?

December 9, 2013, 6:14 am

≫ Next: Nios II Hello World Small Build/Compilation Error

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Hello,
I met an issue when develop PCIe card.
my design is on the basis of Qsys DDR3 reference design.
I found 1 times DMA transfer from FPGA to PC host only support max 256k byte.
I need enlarge to 2M byte during 1 times DMA.
which parameters need to modify?

Thanks in advance.
13011010317

Attached Files

• Why_1_times_DMA_transfer_only_support_256K_byte.pdf (467.7 KB)

Nios II Hello World Small Build/Compilation Error

December 9, 2013, 10:04 am

≫ Next: EyeQ Contour Support

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Hello All,

I am new to using the Nios II Embedded Processor and I am trying to create a new Nios II Application with the "Hello World Small" template just to learn and get familiarized with the tool. I am currently using Nios II 13.1 Eclipse SBT version. When I tried to build the project, I got the following errors:

make: *** [NiosII_Test2_HelloWorldSmall2.elf] Error 1 NiosII_Test2_HelloWorldSmall2 C/C++ Problem
undefined reference to `ALT_MODULE_CLASS_null_write' alt_putstr.c /NiosII_Test2_HelloWorldSmall2_bsp/HAL/src line 51 C/C++ Problem
undefined reference to `null' alt_putstr.c /NiosII_Test2_HelloWorldSmall2_bsp/HAL/src line 51 C/C++ Problem

C:\...\...\...\...\...\software\NiosII_Test2_Hello WorldSmall2_bsp/HAL/src/alt_putstr.c:51: undefined reference to `null'
C:\...\...\...\...\...\software\NiosII_Test2_Hello WorldSmall2_bsp/HAL/src/alt_putstr.c:51: undefined reference to `null'
C:\...\...\...\...\...\software\NiosII_Test2_Hello WorldSmall2_bsp/HAL/src/alt_putstr.c:51: undefined reference to `ALT_MODULE_CLASS_null_write'
collect2.exe: error: ld returned 1 exit status
make: *** [NiosII_Test2_HelloWorldSmall2.elf] Error 1

In my BSP>HAL>src folder, it seems that the error is flagged under the "alt_putstr.c" file with this line of code marked: return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0);

I tried referring to http://www.alteraforum.com/forum/showthread.php?t=5956, but I couldn't find the location that was specified in this thread.

Thanks for the help in advance.

EyeQ Contour Support

December 9, 2013, 2:33 pm

≫ Next: Stratix V GT tranceivers with unmodified output

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I would like to know if any Altera FGPA family support EyeQ Contour (Diagram) at data rates from 122.88Mb/s to 491.52 Mb/s? If so, which?

Best Regards, Richard

Stratix V GT tranceivers with unmodified output

December 9, 2013, 5:43 pm

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Can the PRBS (or a LUT perhaps) be output on a GT transceiver without it going through any serialiser modification?
I would like to modulate a device at up to 20GHz with a PRBS pattern. The Stratix V GT Signal Integrity Dev Kit looks on the surface to be just the thing but I can't determine whether or not the prbs pattern is modified or not. The way I interpret the data sheets, the prbs sequence will be modified in order to provide better signal integrity and voltage balance on the wire. Can this be bypassed to get just the prbs pattern out on the wire, or are all tx pin outputs always "serialised"?

Kind Regards
Neil.

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BCH vs. Reed-Solomon error correction

December 9, 2013, 8:16 pm

≫ Next: Using Nichestack in Superloop mode

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Modern MLC flash devices require that a large number of errors be corrected (up to 32 or even 40). BCH error correction is usually suggested or assumed. However, there don't seem to be any BCH cores available, even though the BCH algorithm is clearly embedded in other IP which is available. Does anyone know why BCH cores aren't available?

We at Octera have developed a BCH core, but having done so, and comparing it to Reed-Solomon, it appears to me that Reed-Solomon may be the way to go instead of BCH. The key is to generate a Reed-Solomon core with a symbol wider than the usual 8 bits. For example, with 12-bit symbols, the message can be up to 4095 symbols long which is 4095*12 = 49140 bits. That is long enough to handle a flash page. The number of errors can be set to 32 by using 64 check symbols. Although this is overkill since it can correct 32 symbols when only 32 bits were needed, it is acceptable. In spite of this overkill, a Reed-Solomon decoder uses fewer gates than a BCH decoder.

So, the second question: Does anyone know why Reed-Solomon isn't used and recommended for flash error correction?

Thanks

Laury
Octera Corp.
laury.flora@octera.com

Using Nichestack in Superloop mode

December 9, 2013, 8:21 pm

≫ Next: Generating an ultrasonic (40 KHz) square pulse for a distance sensor with VHDL

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I have download this superloop example from http://www.alterawiki.com/wiki/Super...et_Server_Plus

and download 20110828_superloop_sss_plus_3c120_marvell_11.0sp1. tgz as i am using Quartus 11.0 SP1

and unzip the archive using tar -xzf <file name>, then run the script from software_example folder that is ./create-this-app using bash (having gcc4).

at the end of this script run , i got error message and not able to create example software.

i am doing all these stuff on D:\ drive and folder name have no space (as mentioned in alterawiki page)

Regards

J S Hyanki

Generating an ultrasonic (40 KHz) square pulse for a distance sensor with VHDL

December 9, 2013, 10:58 pm

≫ Next: Pseudo Random Bit generator with VHDL

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May anyone give me a hint how to generate a square pulse with VHDL to transmit it in a transducer for a distance sensor.

Thanks

Francisco.

Pseudo Random Bit generator with VHDL

December 9, 2013, 11:04 pm

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May anyone give me a hint how to create a Pseudo Random Bit Generator with VHDL and/or Block Diagrams with an ALTERA DE2 Board for a Distance Sensor. The "Random" bits are to be used to generate a set of bits to transmit a supersonic signal through a transducer. The goal is to build a distance meter with VHDL and Block Diagrams through the ALTERA board and QUARTUS.

Thanks.

Francisco

Qsys, System Console, running ethernet loopback issue

December 9, 2013, 11:14 pm

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Hi,

I am using Stratix 5 FPGA development kit. I am trying to check ethernet loopback test mentioned in the

"an647_Single-Port Triple-Speed Ethernet_onboardPHY_RefGuide.pdf".Also we have downloaded the required RTL from the Altera website, compiled the design & downloaded the .sof file.
We followed the instructions mentioned in the above document. But when i am configuring the PHY
through config.tcl script, it shows PHY Link down and other messages shown below.

% source config.tcl
================================================== ============================
Starting TSE MAC Configuration System Console
================================================== ============================






Info: Opened JTAG Master Service






Info: Configure TSE MAC




TSE MAC Rev = 0x00000d00
TSE MAC write Scratch = 0xaaaaaaaa
TSE MAC read Scratch = 0xaaaaaaaa
Command Config = 0x0000803b
MAC Address 0 = 0x22334450
MAC Address 1 = 0x0000ee11
Frame Length = 0x000005ee
Pause Quanta = 0x0000ffff
RX Section Empty = 0x00001ff0
RX Section Full = 0x00000010
TX Section Empty = 0x00001ff0
TX Section Full = 0x00000010
RX Almost Empty = 0x00000008
RX Almost Full = 0x00000008
TX Almost Empty = 0x00000008
TX Almost Full = 0x00000003
MDIO Address 0 = 0x00000000
MDIO Address 1 = 0x00000000
Regiter Status = 0x00000000
TX IPG Length = 0x0000000c
TX Command Status = 0x00000000
RX Command Status = 0x00000000


Info: Closed JTAG Master Service




================================================== ============================
Starting Marvell PHY Configuration System Console
================================================== ============================


Info: Opened JTAG Master Service


Info: Configure On Board Ethernet PHY Chip


Configure PHY.
Set PHY SPEED to 1000Mbps
Enable PHY Auto-Negotiation
Enable PHY In Full Duplex Mode
PHY read Control Register = 0x00001140
PHY read AN Advertisement Register = 0x00000001
Advertise PHY 1000BASE-T Full Duplex
PHY read 1000BASE-T Control Register = 0x00000e00
Set PHY Synchronizing FIFO to maximum
Set PHY HWCFG_MODE for SGMII to Copper Without Clock
PHY read Extended PHY Specific Status Register = 0x00008484
PHY Link Down!
PHY Speed and Duplex Resolve Failed!
PHY operating in Half Duplex mode.
PHY operating Speed 1000Mbps


Info: Closed JTAG Master Service




================================================== ============================
Starting TSE PCS Configuration System Console
================================================== ============================


Info: Opened JTAG Master Service


Info: Configure TSE PCS


TSE PCS rev = 0x00000d00
TSE PCS write scratch = 0x0000aaaa
TSE PCS read scratch = 0x0000aaaa
TSE PCS if_mode = 0x0000000b
TSE PCS control register = 0x00001140
Waiting Link Up.....
Link is established!
Partner Ability:


Copper link interface is down.
Copper operating in Half Duplex mode.
Copper operating Speed 10Mbps


Info: Closed JTAG Master Service



Please let me know if i am missing anything in proper configuration.Also find attached the design for your reference.
Please also check from your side and let us know the feedback at the earliest possible time.
Thanks in advance.

Attached Images

• lpkbk_fail.jpg (73.8 KB)

Attached Files

• an647_Single-Port Triple-Speed Ethernet_onboardPHY.qar (3.81 MB)