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Enabling generic tri-state controller kills NIOS

December 11, 2013, 1:46 pm
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So, I have a basic NIOS project. It builds; meets timing; blinks an LED; it works. Nothing earth shattering.

However, I'd like to access my flash. The QSYS way is to use the generic tri-state controller. Fine. I instantiate a generic tri-state controller, hook it up, and rebuild.

Dead. The basic init logic seems to work--my LED's come on and stay on (they do not do that until the FPGA is programmed).

However, the system can't even get the system hash or timestamp via JTAG. It probably never comes out of reset.

The *ONLY* difference is that I check or uncheck the "Use" checkbox on the tri-state controller and the hit generate. If I use the controller, the system is dead. If I do not use the controller, the system works fine--I get the hash, the timestamp, and my LED's blink.

Suggestions for how to debug this? QSYS file attached.
Attached Files
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How to check clk and reset signal when ELF downloading failed?

December 11, 2013, 2:10 pm
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I learnt from the forum that an ELF downloading failure is likely to be caused by an incorrectly set clk signal or reset signal. The problem is how I can check the clk or reset signal without running the nios program?

My design is a qsys project consisting of nios, some peripherals including external ddr-ram controller and a custom module connected through avalon-mm bus. The system works under a single clock domain generated by the pll that comes with the ddr-ram controller. Reset signal is connected to LOW directly.

Timing requirement was met with some unconstrained paths (input/output ports and paths) which should be fine because previously a similar system ran successfully with these paths unconstrained. Any suggestion will be appreciate.

Thanks guys.
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EPCS vs. EPCQ and JTAG UART (questions on .sof and .pof files, too)

December 11, 2013, 2:30 pm
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Hi Everyone,

I have a Cyclone IV EP4CE22F17C7N FPGA on the board that I'm working on and I am confused on the whole EPCS/EPCQ/JTAG-UART configuration of the FPGA.

On my Qsys system, I have:
Nios II Processor
On-Chip Memory
2x PIO
EPCS_flash

When I am using Nios II SBT, I tried programming/configuring the FPGA through Nios II's "Quartus Programmer" with my USB blaster plugged into the JTAG port of my board. I found the .sof file that I had used for my project and programmed the FPGA through Nios II this way. Am I doing this wrong? Am I supposed to use the Active Serial port when I'm programming with EPCS? When I try to switch over the USB Blaster to the Active Serial port to program it that way (in Quartus II), I have to add a device and I don't know which one to choose (EPCSx/EPCQx, x=1,4,16,64,128). Also, do I need to include a JTAG-UART component in my Qsys system?

I tried reading all of Altera's documents on JTAG-UART and EPCS/EPCQ and I got confused...

Also, when I tried to debug the app (Right click app>Debug As> Nios II Hardware) with the USB blaster plugged in to the JTAG port, I tried to check the system ID properties and for all of the criteria (expected system ID base address, expected system ID, connected system ID, expected system time stamp, and connected system timestamp) everything is listed as "Not Found". I had to check the "Ignore mismatched system ID/timestamp" boxes in the Target Connection tab to get my program to build successfully.

Anyways, I hope this makes sense. Thanks for your help. I really appreciate it...
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Getting started with a 3 port ethernet design

December 11, 2013, 2:41 pm
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I am looking for any links and references to get started designing the following:

Source Synchronous Parallel data input
UDP packetized output to 3 locations @ 1000mbps

I believe my setup will get me there with some work but any references would be helpful to figure this out.

Cyclone IV GX dev kit with HSMC Dual port gigabit adapter

I assume I'll need to make use of TSE MAC and Nichestack IP.

My plan is to fill a buffer with the parallel data and output a UDP packet when the buffer fills to a predetermined number of bytes. Any app notes I should read, any pitfalls to watch out for?

Thanks!
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SD Card Core IP with Nios II

December 11, 2013, 4:15 pm
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Hi,

I am trying to interface an SD card with the FPGA (Cyclone IV EP4CE22F17C7N) on my board using the SD Core IP provided by Altera's University Program and the Nios II Embedded Processor. I am not using a development board.

My Qsys design contains:
Nios II Processor
UP SD Card Core IP
EPCS Flash
LED IO
PIO


I am very new to this "network-on-chip" or "system on programmable chip" concept, and I am finding it hard to start... I've already designed a Qsys system and instantiated it in my top-level design in Quartus II. The last thing I have to do is to get the Nios II processor to talk to both the SD card and my FPGA, but I don't know what to do. I'm familiar with HDL coding, but I'm fairly new to coding in general, and I have no idea where to start with the C code. I've tried reading all of the different documents that Altera has provided about Nios II, Qsys, etc., but I don't think it helped much. So, please bare with me as I'm sure my questions are going to sound very trivial to most of you.

How do I connect the variables written in the Nios II C code to the variables in my top level design? Do I start coding in the main C file? If any of you have an example of the Nios II system/software that you created for your board (development board or not) using the SD card core, I would be VERY appreciative if I look at it for a reference.

Many thanks!
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Help with latches but can't figure out why after several checks

December 11, 2013, 4:33 pm
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Hi all can someone figure out why this code gives the following error in Quartus II (vs 13):

It's about finite state machines with keys, ledG, ledR and 5 states (opened, closed, locked, unlocked, error):

Here comes the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity VHDL_uppgift_4c is
port (
clk : in std_logic; -- sync clock signal
reset_n: in std_logic; -- async reset signal
key_0 : in std_logic; -- door open input button
key_1 : in std_logic; -- door closing button
key_2 : in std_logic; -- button pressed and door locks
key_3 : in std_logic; -- button pressed and lock opens
LED_out: out std_logic_vector(1 downto 0);
LED_R: out std_logic_vector(2 downto 0)

);
end VHDL_uppgift_4c;

architecture final_syn of VHDL_uppgift_4c is
type state_type is (closed, opened, locked, unlocked, error); -- register to hold current state
signal current_state, next_state : state_type; -- defination of register of inner states


-- state register
begin
process (clk, reset_n)
begin
if reset_n = '1' then -- async reset of machine
current_state <= closed; -- default state after reset
elsif (rising_edge(clk))then -- sync part of machine
current_state <= next_state;
end if;
end process;


process(current_state, key_0, key_1, key_2, key_3)


begin


case current_state is
when closed =>
if key_0 = '1'then
next_state <= opened;
LED_out <= "00";
else
next_state <= closed;
LED_out <= "01";
end if;




when opened =>
if key_1 = '1' then
next_state <= locked;
LED_out <= "10";
else
next_state <= opened;
LED_out <= "11";
end if;

when locked =>


if key_2 = '1' then
next_state <= unlocked;
LED_R <= "000";
else
next_state <= locked;
LED_R <= "001";
end if;


when unlocked =>
if key_3 = '1' then
next_state <= unlocked;
LED_R <= "010";
else
next_state <= error;
LED_R <= "110";
end if;


when error =>
if key_3 = '1' and key_0 = '1' then
next_state <= error;
LED_R <= "101";
else
next_state <= opened;
LED_R <= "111";
end if;


--when others =>
--next_state <= error;


end case;
end process;
end final_syn;
--------------------------------------------------------------------------
Error message reads:

Warning (10631): inferring latch(es) for signal or variable "LED_out", which holds its previous value in one or more paths through the process
Warning (10631): inferring latch(es) for signal or variable "LED_R", which holds its previous value in one or more paths through the process

____---------------------------
Thanks for helping out
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setting default modelsim.ini path in altera modelsim 6.5e

December 11, 2013, 6:29 pm
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Hi,

How do i set default path for modelsim.ini file in altera modelsim 6.5e? which is under "copy settings from" when a new project is created. and also how do i setup the default path for project location.

thanks
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Problem programming CPLD with multiple devices in the JTAG chain, error 209055

December 11, 2013, 8:10 pm
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I'm having a problem getting my Altera CPLD (EPM2210) to program using the Quartus II Programmer. My JTAG chain has four devices in it, three Xilinx FPGAs and the Altera CPLD. I've imported the BSDL files for the Xilinx parts and the programmer successfully detected the chain. I assign the .jam file I want to program the CPLD with to the CPLD. All the other devices show "<none>" in the File column. When I hit "Start", it immediately says "(Failed)" in the progress bar. In the Quartus II System tab, it gives the error "209055 Multiple files specified in Programmer". I'm using a usb-blaster.

I looked into using the command line tool "quartus_jli" but I didn't see an option to specify which device in the chain I wanted to program.

Any help would be appreciated.
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hps in qsys

December 11, 2013, 9:21 pm
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Hello.
Somebody enlighten me about the use of hps in qsys.
When I add hps in qsys, I need to specify the ports, that are connected to the memory, and its parameters. Do I understand correctly that this is necessary to possible use hps memory in fpga (using fpga2hps sdram)? if not, what does it do? And if so, how to avoid these settings if I do not plan to use this feature. Thanks.
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Unable to Program EPCS16 in system

December 11, 2013, 9:41 pm
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I recently designed and put together my first FPGA board. I can configure the FPGA over JTAG fine, but the EEPROM seems out of reach. If I use the USB-Blaster in AS mode, it fails to get the device ID, and if I use a .jic file, the process fails, with no explanation. Other than that, the board behaves as desired (so far).

I'm using an EP4CE22E22C8N with an EPCS16 flash chip. They are configured as shown in the Cyclone-IV Handbook on pp. 218. I can configure the FPGA over JTAG, however I cannot configure the EPCS16 over JTAG or the AS header. I've attached the configuration page from my schematic.

Thanks for any help.
Attached Images
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speed up read of embedded RAM from external bus interface

December 12, 2013, 1:53 am
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Hi all!
My FPGA (CycloneII) is a slave on an MCUs external bus interfaces (EBI). The MCU shall read the content of FPGAs embedded RAM preferably without wait state. Unfortunately I don't know yet now to get the logic fast enough. The EBI is operated at 60Mhz and the FPGA has a 166.7Mhz clock. I've used the FPGA clock to clock the RAM. The address lines are permanently connected to the RAM. The Output to the EBI is done using unclocked logic. Using SignalTap I can see, that data from the RAM is updated one clock cycle after address changes. But the data needs an other clock cycle be be visible for the MCU. So I guess, there are some timing constraints missing between the FPGAs clock and the data output pins. I've studied AN433 but didn't found the point.
Can anyone please advice now to speed-up the interface? Thank You!

Pauliman
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graphics lcd controller

December 12, 2013, 2:32 am
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hi, pls reply me if any one knows. i had requested for a vga controller core but instead they have sent me a graphics lcd controller core is it same as vga controller. or can i use graphics lcd controller instead in my project to display the image i capture from camera. pls tel me if anyone knows pls i am stuck right now
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Data transfer between FPGA and OMAP-L138 via Universal Parallel Port (uPP)

December 12, 2013, 3:39 am
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Hi,

Did anyone transfer data from FPGA to OMAP-L138 EVM via uPP ? The OMAP-L138 has a Universal Parallel Port (uPP) which offers a high-speed parallel data bus with several important features. But the problem is that I couldn't find any expansion connector for uPP pins to make the physical connection with FPGA.

Attached is the snap of OMAP-L138 EVM, expansion connector which has uPP signals can be seen at the bottom right hand corner of the screen.
http://e2e.ti.com/cfs-file.ashx/__ke...8_2D00_Exp.JPG

I appreciate if anyone can help me with this.

Thanks.
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Bumping on this!! Help error message in Quartus II

December 12, 2013, 3:59 am
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Hi guys can someone figure out why Quartus II gives me the following error messages without me assigning anything to the .qsf file:

Error message is below:

Error (125048): Error reading Quartus II Settings File C:/altera_trn/VHDL_uppgift_4e/VHDL_uppgift_4e.qsf, line 41
Info (125063): set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst "
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125080): Can't open project -- Quartus II Settings File contains one or more errors
Error: Quartus II 64-Bit Hierarchy Elaboration was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 381 megabytes
Error: Processing ended: Thu Dec 12 12:47:21 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00

Thanks for any help offered:oops:
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Errors trying to instantiate flash in SOPC Builder

December 12, 2013, 4:01 am
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I'm trying to instantiate a flash device in SOPC Builder.

I instantiate the Flash Memory Interface(CFI) with a template of Intel 256P30. I instantiate my Avalon-MM Tristate Bridge. I hook them up and get the following error:

Error: cfi_flash_0.s1: Master tri_state_bridge_0.tristate_master does not have a waitrequest signal. Slave must match master's read and write wait time (read:0 write:0)
Error: tri_state_bridge_0.tristate_master/cfi_flash_0.s1: Signal tri_state_bridge_0.tristate_master[0] and signal cfi_flash_0.s1[16] must have the same data width


Any suggestions?


Version is Quartus 12.1sp1
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Compiler Warnings

December 12, 2013, 4:03 am
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I am developing an n linear sorter using n work-items. Therefore, I am using two barrier(CLK_LOCAL_MEM_FENCE) to ensure that compares and shifts are done properly. My code works on FPGAs and GPUs.

I am a bit confused by this AOCL warning:

"Compiler Warning: Threads may reach barrier out of order - allowing at most 2 concurrent workgroups"


I thought threads (work-items) reaching a barrier out of order is OpenCL default behaviour or can we assume that on FPGA the work-items within a work-group are always implemented in a lockstep manner? Further, is the compiler trying to implement concurrent work-groups?


Thanks
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about NIOSii 12.1 vs multi-core

December 12, 2013, 5:15 am
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Hi, I run the NIOSii 12.1 appear with one question,I have two cpu,then I wish my SOPC can do multi-core. I use Launch Group(Run-configuration-Launch Group).I already add two cpu to Launch Group,but two CPU can't execution at the same time.It can that one by one run cpu. So, How can I do that can execution at the same time.
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Filling in cyg_flash_devtab[] array

December 12, 2013, 5:16 am
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Does anybody know when and how cyg_flash_devtab[] array is filled in? I see &(syg_flashdevtab[0]) == &syg_flashdevtab_end and syg_flashdevtab[0].num_block_infos < 0 whereas SYGHWR_IO_FLASH_DEVICE == 1
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using epcs flash for both reset vector and store configuration

December 12, 2013, 6:29 am
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Hello all,

I've tried to make a system in which the EPCS device would hold basically all information required for a working equipment. When implementing it, I couldn't open the EPCS device in NIOS software.
I've read here http://www.alteraforum.com/forum/showthread.php?t=21484 that if I use the EPCS to hold both firmware, software and configuration it won't work.

I'm using Quartus and Nios 9.0.

Is there a way to make it work? or I just need to add two separated devices?


thanks,
Alex
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Negative Slack after constraing the clocks

December 12, 2013, 6:31 am
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Hello,

I have a design with a couple clocks that i constrained on TimeQuest, but they still show negative slack on Hold.

I ran the analysis and synthesis first, then ran TimeQuest, checked the box for running "Post Mapping" and "Zero IC Delay". Does that mean that my clocks won't work in this design?

My SDC file:

Quote:
#************************************************* *************
# Time Information
#************************************************* *************

set_time_format -unit ns -decimal_places 3

#************************************************* *************
# Create Clock
#************************************************* *************

create_clock -name {inclk} -period 20.833 -waveform { 0.000 10.416 } [get_ports {inclk}]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[1]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[1] }]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 20.833 -waveform { 0.000 10.416 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]
create_clock -name {spi_clk} -period 20.833 -waveform { 0.000 10.415 } [get_ports { spi_clk }]
create_clock -name {hbi_clock_generator:inst23|inst} -period 250.000 -waveform { 0.000 125.000 } [get_registers { hbi_clock_generator:inst23|inst }]
create_clock -name {hbi_clock_generator:inst23|counter:counter48MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter48MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]

#************************************************* *************
# Create Generated Clock
#************************************************* *************

create_generated_clock -name {pll|altpll_component|pll|clk[2]} -source [get_pins {pll|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inclk} [get_pins {pll|altpll_component|pll|clk[2]}]
PS: is there a tag for code in this forum?
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