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FPGA as router delay simulmator

December 12, 2013, 7:09 am
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Altera staff,

I'm new in this forum and I need your help.
okay, I'm looking for peroforming the following application:


I have a number of devices which communicate to each others through analog signals.
what I'm looking for is to use an FPGA bywhich I can interface my devices.


To be clear, with theyour product I should be able to do:
- routing received signal from one device to another
- delaying some signals in specific instance
- using a software interface to perform the desired specifcation.
- I need at least 10 analog inputs and 3 analog outputs.


Specs:
-The analog signal input frequency is about 24KHz
- the delay range is about 0 to 25µsec
- voltage range is +/- 10V for analog inputs and +-5V for the outputs


my questions:
what's the FPGA type that answers to my applications ?



Best Regards.


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DE4 Simple Server Socket example

December 12, 2013, 7:10 am
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Hi,
I have an Altera DE4 Development and Education Board. I’m using Quartus II 11.0.
I’m trying to run “Simple Socket Server (RGMII)” example.
This is the ‘Nios II Console’ output:

=============== Software License Reminder ================
This software project uses an unlicensed version of the NicheStack TCP/IP
Network Stack - Nios II Edition. If you want to ship resulting object
code in your product, you must purchase a license for this software from
Altera. For information go to: "http://www.altera.com/nichestack"
================================================== ===
InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Your Ethernet MAC address is 00:07:ed:ff:ed:15
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x05101800
INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : Extended PHY Specific Status Register = 0x0001
INFO : PCS[0.0] - Configuring PCS operating mode
INFO : PCS[0.0] - PCS SGMII mode enabled
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 192.168.1.234
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)
InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Can't read the MAC address from your board (this probably means
that your flash was erased). We will assign you a MAC address and
static network settings

Please enter your 9-digit serial number. This is printed on a
label under your Nios dev. board. The first 3 digits of the
label are ASJ and the serial number follows this.
-->Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)

123456789
123456789
Your Ethernet MAC address is ff:ff:ff:ff:ff:ff
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x05101800
INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PCS[0.0] - Configuring PCS operating mode
INFO : PCS[0.0] - PCS SGMII mode enabled
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=89, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)

After this message, I try to connect via telnet to the board, but nothing happens.

Can you help me, please?

BR,
Umberto
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Are Stratix V IOE delays programmable dynamically?

December 12, 2013, 7:16 am
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Are Stratix V IOE delays programmable dynamically? The documentation I found so far seems to say that the delays are programmable but it seems you set the delay once at compile time and it doesn't change. I'm familiar with the Xilinx system where there is an I/O delay element with clock/increment/reset input that allows the delay to change on the fly. The I/O to external memories is calibrated using this. I was not expecting to see that the IOE delays on the Stratix V were static. If they are I wonder how dynamic calibration works.

If anyone can correct me or give insight I'd appreciate it. Thanks.
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Newbie - FT245 driver and 1 second period timer issue

December 12, 2013, 7:22 am
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Hello,

I am a newbie in FPGA programming and VHDL, however I did some projects on Altera boards (simple 7 segments, etc).
I am using wayengineer.com Cyclone IV board and FT245 breakout board for it. It runs on 50Mhz clock.
I did a code that can read a single byte from the FT245 and then it will send it back.
Problem is that every 1 second, I want the data - last byte received to be sent back. However, code constantly sends data out. It does read it correctly, so if you type 'a' it will send 'a' all the time and not when PeriodS_Reg = '1'.
Debug led that blinks every 1 second, does blink in that interval.
If I comment out in idle state elsif(PeriodS='1') and in reading_end I go to writing_prepare state, code correctly echo's back the last read character.
So I think this elsif(PeriodS='1') in idle state is the problem since it always goes in it.

Do you have any suggestions?
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Quartus II 13 problem! bumping on this one

December 12, 2013, 7:36 am
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Hi guys can someone figure out why Quartus II gives me the following error messages without me assigning anything to the .qsf file:

Error message is below:

Error (125048): Error reading Quartus II Settings File C:/altera_trn/VHDL_uppgift_4e/VHDL_uppgift_4e.qsf, line 41
Info (125063): set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME "VHDL_uppgift_4e_vhd_tst " -section_id "VHDL_uppgift_4e_vhd_tst "
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125022): Section identifier missing or not required
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst -section_id eda_simulation"
Info (125063): set_global_assignment -name EDA_TEST_BENCH_NAME "VHDL_uppgift_4e_vhd_tst " -section_id eda_simulation
Error (125080): Can't open project -- Quartus II Settings File contains one or more errors
Error: Quartus II 64-Bit Hierarchy Elaboration was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 381 megabytes
Error: Processing ended: Thu Dec 12 12:47:21 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00

Thanks for any help offered:oops:
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MSEL clarification for Cyclone III - AS Mode (single device, EPCS) & "sanity check"

December 12, 2013, 2:14 pm
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Hi all,
Here's a set of "sanity check" questions on a problem we have: We have a custom board using a single Cyc III part, and have been running a version of it with PS mode, and now have updated the board with EPCS and running AS Mode.

Quartus Programmer (v12, also v11) can program the EPCS on our board (it says it's successful). We PoR the board, and it doesn't enter User Mode. We see on logic analyzer the signals nCONFIG and nSTATUS go High, indicating end of Reset phase. But we don't see the nCSO go Low, nor do we see the DCLK or ASDO lines change.

We've checked all the usual suspects (board signal routing, consistency of assignments between Quartus pinout and PCB lines, etc.), and the only thing that gives us pause is the MSEL connections. The signaling we see on the logic analyzer reminds us of PS mode rather than AS mode.

Our Cyc III package doesn't have MSEL[3], and we have MSEL[0] and MSEL[1] driven to GND, for AS mode. The MSEL[2] is connected to VCCINT (1.2v) instead of VCCA (2.5v), which is a problem. We made a quick board change with a resistor so that we could bring VCCINT up to 1.8v, hoping to meet the threshold for this MSEL2.

According to Table 9-7 (Cyclone III Handbk), MSEL bit pattern of 1000 indicates an Active Parallel mode, and 0000 indicates Passive Serial mode; whereas what we want is MSEL = X100 Fast Active Serial Fast mode, assuming the bit-3 is treated as a don't care.

So, the questions are these:

(1) Given that our Cyc III package doesn't support MSEL3, how does the FPGA internal logic treat the don't care status of the MSB of MSEL[3:0]? I can't find any discussion of this anywhere. But the Table 9-7 in Cyc III Handbk is misleading in that it infers one should be able to map all MSEL bits. Does the Cyc III assume MSEL3 is either 0 or 1, or does it treat it a a don't care. Or, does it make a determination as to which mode in indicated with bit-3 based on the listed configuration voltage in Table 9-7, meaning I can change the mode selection based on the voltage level, when I don't have MSEL[3]?

(2) If we're attempting to run the MSEL[2] pin at 1.8v, shouldn't we be able to drive the voltage threshold for the FPGA to interpret that bit to be a logic 1 (thereby indicating that we want AS rather than PS mode)? Note that we're attempting a workaround fix for now, just to get the board to program from EPCS.

(3) Our whole hypothesis as for why the board isn't working is based on the notion that the FPGA is thinking that it should come up in PS mode rather than in AS mode, and that this is why we're not seeing nCSO, DCLK or ASDO signaling from FPGA to EPCS to start configuration phase. Is this a reasonable hypothesis? Anyone have similar experiences?

Lot of stuff here. Thanks for reading and for any cogent thoughts you might have, dear reader.

regds,
jim
Attached Images
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EPCS config failing advice needed

December 13, 2013, 2:28 am
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Morning folks,

I have just created my first FPGA (EP3C10E144C8N)board with a config memory (AT25DF321A-SH-B). Whilst I seem to be able to program the device with the jic and then verify it, the FPGA does not configure. If i make a change to the program and then compile etc and verify it spots the difference and fails verification, which suggest to me that this device is at least capable of communicating during programming.

After reset and the FPGA starts to look for configuration I examine the nCONFIG, nSTATUS, CONF_DONE signals and find that the nSTATUS pin is toggling suggesting to me that (according to p 9-9 of the cyclone II handbook) that it is failing configuration and attempting to start itself again, and doing so repeatedly! CONF_DONE is low (which stands to reason if it hasnt configured) and nCONFIG is high (which again is what i would expect to see).

I have initially told Quartus and the jic conversion process that the config device is an EPCS16. I can only assume that the device is not working as I expect even though I was able to program and verify the jic file to the memory device.

Is this true, that whilst it may program and verify ok it still might not configure the FPGA?? Would i be better of with M25P16 device???

Any comments would be most welcome.
MEM CONFIG 1.jpgMEM CONFIG 2.jpg
deBoogle

PS couple of waveforms showing nSTATUS on CH1, and the CLK on dig CH0, SO on dig CH1 and SI on dig CH2
Attached Images
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How to keep all top level signals for mapping to pins (feasibility study)

December 13, 2013, 4:34 am
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Hello,

For a feasibility study, I have to see if we can use a certain FPGA. Mainly seeing if we can fit all the needed signals on the pins.

For that I took another project on which the new project will be based. Removed all the code and left the toplevel signals which need to be mapped on the pins. I also kept all needed pin assignments.

It does it synthesis and elaboration well but when it comes to the fitter, I get following error (for multiple pins):
Error (177035): The input pin tmds0_rx_dp[0] assigned to HSSI Pin_V34 has no fanout.
Error (177035): The input pin tmds0_rx_dn[0] assigned to HSSI Pin_V33 has no fanout.

How can I overcome this error? I tried adding the preserve_fanout_free_node attribute on these pins. I tried adding an iobuf_diff for these differential signals and noprune on their output. But nothing helps.

Does somebody know how to overcome this? Or help me in the right direction for such a feasibility study?

Thanks a lot in advance!
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DDR3 UniPHY IP synthesis problem

December 13, 2013, 4:59 am
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Hi!
When I tried to compile the example_project generated in the DDR3 UniPHY IP, I found some warnings in the synthesis procedure. This one confused me:
Warning (14285): Synthesized away the following PLL node(s):
- Warning (14320): Synthesized away node "ddr3_example_if0:if0|ddr3_example_if0_pll0: pll0|pll_mem_clk"
- Warning (14320): Synthesized away node "ddr3_example_if0:if0|ddr3_example_if0_pll0: pll0|afi_phy_clk"
Does it matter my ddr3_project working?

I'm not familiar with the intersignals between the memory controller portion to the UniPHY portion, but I think if afi_phy_clk is synthesized away, some commands and data cannot transmit to the external memory.

Thanks a lot!
BR,
Song.
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Standard Ethernet example cpu generation issue

December 13, 2013, 5:03 am
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Hi,
I am trying to regenerate the standard ethernet design useing quartus webpack 12.0 sp2 and I get the following errors when I generate the niosii-ethernet-standard-3c25/eth_std_main_system in Qsys. What am I doing wrong?
Error: cpu: Failed to generate module eth_std_main_system_cpu
Info: cpu: Done RTL generation for module 'eth_std_main_system_cpu'
Info: cpu: "eth_std_main_system" instantiated altera_nios2_qsys "cpu"
Error: Generation stopped, 74 or more modules remaining
Info: eth_std_main_system: Done eth_std_main_system" with 36 modules, 16 files, 949361 bytes
Error: ip-generate failed with exit code 1: 2 Errors, 7 Warnings
Info: Finished: Create HDL design files for synthesis
Attached Files
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IC delay between Global clock buffer to IOBUF causing timing violations

December 13, 2013, 2:36 pm
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Hi

I am trying to fix timing violations on my design, IC delay between global clock buffer to IOBUF is causing a negative slack of -1.698. I have tried to instantiate regional clock buffers instead of global clock buffers then i am running in to data path delay since option "FAST_INPUT REGISTER ON" to data ports is getting ignored.

Any suggestions how to fix this.
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HSR/PRP implementation project, which board is suitable

December 13, 2013, 4:45 pm
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hello,
i am student in communication field. i am looking to make development on the high seamless redundant protocol (HSR). i would like anyone that can advice me what is the best first step to do. and if altera helps me or not.
what i want is FPGA card suitable for academical budget that contain at least 4 ethernet ports, in order to make possibilities to make all HSR nodes from danh to redbox and quad box.
Speed of this ports supports tri speed 10/100/1000 mbps or only 10/100.
and does altera give any certain of plans or design manuals?
thank you so much
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GSM and GPS module for FPGA

December 13, 2013, 10:43 pm
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Hi,i would like to know what the spec of GSM and GPS module that compatible with altera board because my project concern with GSM and GPS module.Altera have supply for GSM and GPS module or not?because i'm afraid if i used the others module will not compatible with my altera board.Hope altera can help me.Thank you:)
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eclipse functions

December 14, 2013, 6:32 am
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Hello everybody;
where I can found the datasheet which discuses the functions used in eclipse such as "IORD() OR IOWR() ,TIMES(),,,etc".
thanks.
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FIR compiler - filter interconnection

December 14, 2013, 10:45 am
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Hi everybody,

Have anyone from the skilled users used the FIR filter in the application? I understand the filter features the FIR issues etc.

Now I am in the following stage:

I have working Qsys system with the processor, NIOS, SDRAMs, PIOs...
What is the goal? I want to filter the PIO data (ADC output) and for easy understanding send to the output PIO (DAC input) with the same bit-width.

I do not know how to convert the PIO port to the streaming source/sink of the FIR compiler?

Thanks for hint.

Jan.
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accesing a custom component

December 14, 2013, 12:35 pm
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Hello every body;
I have created my custom component, it have an avalon slave interface, it have 2 slave registers, how can i access these registers if i have the base address, i mean that what is the order of these internal registers,
another question is if this component takes 20 clk cycle to finish, how can i take its output when it just finish.
Thanks
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Quartus Web Edition 13.1.0.162 install problem on Debian 64-bit

December 14, 2013, 1:21 pm
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I'm trying to install Quartus 13.1 on a Debian 64-bit system.

Code:
./setup.sh  --version
Quartus II Web Edition (Free) 13.1.0.162 13.1 --- Built on 2013-10-24 05:58:34 IB: 8.6.0-201308221742
Code:
$ cat /etc/debian_version
7.2
Code:
$ uname -a
Linux foobar 3.2.0-4-amd64 #1 SMP Debian 3.2.51-1 x86_64 GNU/Linux
The install works fine until the NIOS-II installation part, where it complains about not being able to install symbolic links. There is nothing unusual about the system or the installation directory (my home directory/altera/13.1) and if I ignore the link creation errors, the install continues until it tries to install the Quartus Help system, where it says it can't execute the command and fails.

I can run the help (and later ModelSim) installers just fine manually.

Is this a known issue? How should I go back and re-create the missing symlinks? Not enough information is given in the error message to allow me to just use ln and create them myself.

Once installed, Quartus seems to function fine, although I have to manually go and install device support since the installer never finishes far enough to install the device support automatically.
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Help in my FPGA assignment

December 15, 2013, 7:37 am
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Hi All

I am new in using FPGA stuff,, I know it may seems a silly question for u,,

but I am looking forward to your help,,

I have a ready FPGA assignment and I just want to upload it on Altera programme and get the results

I compiled it successfully ,, but what should I do after compiling it and how??

I dont know if it is possible to get a private help via emails if u think my question is too silly ,, but I really need help

kind regrds
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How to manually place a component with Quartus II

December 16, 2013, 12:27 am
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How do you manually place a component on a FPGA with Quartus ? i.e. I have the coordinates where I want to put the component on the FPGA, how do I use them with my VHDL code to say to Quartus 'put the component at these coordinates (x,y)' ? Thanks !
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Linux kernel on Cyclone IV GX FPGA

December 16, 2013, 1:36 am
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Hi

I am new to Cyclone IV GX FPGA SoC. Can you please guide me
1. which kernel version and ubootloader version are supported by Cyclone IV GX FPGA Kit.
2. From where, I can download the kernel/uboot sources.


Thanks in Adv,
SaiSenthil.
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