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RYSC Plug: The Slithy Toves

January 28, 2014, 9:01 am
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This has nothing to do with Altera, so can be considered spam, but as a long time poster to this forum, as well as various posts to the wiki like the TimeQuest User Guide, I hope I can get away with it. :)

Basically I'm plugging a book I recently published called The Slithy Toves. It is available as a paperback on Amazon.com or digitally through Kindle(which can be an app on other devices like the Ipad). Here are the shortened links:

Kindle Link:
http:/amzn.com/B00G4MLZUM
Paperback Link:
http:/amzn.com/0615901824

You can also search for The Slithy Toves by Ryan Scoville on Amazon or Kindle.

Anyway, sorry for the unrelated plug.

Thanks,
Ryan
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Quartus archive project from 13.0 does not load in 11.1

January 28, 2014, 9:35 am
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I have archived my Quartus project and generated a ".qar" file. When I restore the project in Quartus 13.0 everything works, but when I try to restore the project in Quartus 11.0 I am receiving an error.

If i copy the whole project folder from 13.0 and use load it in 11.0 on another computer it works fine but project folder is quite large so I would like to use the ".qar" file if possible.

attached is a picture of the error i am receiving.
Attached Images
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ST FIFO question

January 28, 2014, 9:43 am
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Hello,

I need to interface a 16-bit 12MHz AD with a Cyclone II. The data comes from the AD in 8 data ports, it sends the MSB on the rising edge and the LSB on the falling edge of the 12MHz clock. I came up with the following Qsys design: AD > ST FIFO MM > MM DMA MM > ONCHIP RAM. I tried to create it on Qsys but the ST FIFO only acepts 32-bit transfers. My question is, can i still use the ST FIFO and ignore the other bits? Will a MM FIFO work instead of a ST FIFO?

Oh, i also would like to know if a beat is the same as clock transition.

Thanks.
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calculating eigenvectors and eigenvalues

January 28, 2014, 9:45 am
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Hi there,
i have a real,general high order matrix stored in a 2-dimensional array in nios's memory.and i need to find all of its eigenvectors and eigenvalues.
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Modelsim error on compiling Avalon BFM turorial

January 28, 2014, 10:45 am
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Hi,

I am trying to understand how to use the Avalanon Verilog BFM models.

I just generated a testbenhc using Qsys as instructed in the Avalanon BFM tutorial.


When I go to run the simulation I get the following single erro near the end of the compile stage.

Any suggestions on how to fix that appreciated.

Thanks Martin


Top level modules:
# st_bfm_qsys_tutorial_tb
# QuestaSim-64 vlog 10.2c Compiler 2013.07 Jul 18 2013
# -- Compiling module test_program
# ** Error: ./test_program.sv(32): Could not find the package (verbosity_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# ** Error: /net/tcfiler2.scs.agilent.com/vol/v51/rpdhw/tools/mentor/modeltech/10.2c/questasim/linux_x86_64/vlog failed.
# Error in macro /net/tcfiler2.scs.agilent.com/vol/v51/rpdhw/projects/greywolf/mataylor/work/altera-avalon-bfm/ug_avalon_verification/qsys/user_test_program/load_sim.tcl line 12
# /net/tcfiler2.scs.agilent.com/vol/v51/rpdhw/tools/mentor/modeltech/10.2c/questasim/linux_x86_64/vlog failed.
# while executing
# "vlog -sv ./test_program.sv"
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Fitter Error

January 28, 2014, 11:05 am
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When running Fitter(Place&Router), I get the error: Can't place multiple pins assigned to pin location Pin_K22 (IOPAD_X77_Y33_N14)

But when I check my pin planner, there is only one signal assigned to Pin_K22. (screen shot attached)

What can be the possible reason for this fitting error? Thank you.
Attached Images
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Modelsim Error: (vcom-7) Failed to open design unit file "..." in read mode

January 28, 2014, 12:11 pm
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Dear all,

There is an error I need your suggestions:

Error: (vcom-7) Failed to open design unit file "directory/file name" in read mode. Can you inform me how I can overcome it?

I am using ModelSim Altera Starter 10.1d with Quartus II 13.1.

Thanks!
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Looking for I2C drivers info for the Arrow SoCkit.

January 28, 2014, 1:01 pm
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Hi all,

Yes, this is my first project working with the SoCkit, and my first time with Linux as well so I’ve got a lot to learn. I’ve gone through the HW and SW labs, and can boot Linux and attach and run the DS-5 debugger etc. But I haven’t been able to find documentation on how to communicate with the I2c drivers built into the kernel. I don’t want to have to write my own drivers (nor do I think I have to). I’ve looked all over rocketboards.org, Yocto project and Altera’s HWLIB documentation (and many many more Google dead ends). I know there must be a gold mine of information somewhere, or nobody would ever get anything done, but I’m digging in the wrong places. Or maybe I’m looking right at the answer’s but I’m just not seeing them.

I’m using the Poky 8.0 (Yocto Project 1.3 Reference Distro) 1.3 socfpga_cyclone5 kernel.

I did manage to talk to the G-Sensor on the board using straight I2C ioctl/read/write functions:

1) ioctl(file, I2C_SLAVE, chipAddr) // open file
2) write(file, buf, 1) // send read command/address
3) read(file, buf, byteCount) // read data

But this sequences sends a stop-bit between the steps, and the part I’m trying to talk to (an LTC2977 device through the LTC connector) uses the PMBus protocol which is very close to I2C (and SMbus) protocol, but when reading a register I can’t issue a stop-bit after sending the read command or the part won’t respond.

I know the kernel I'm using already has what is needed to talk to this bus, because if I use the i2cdump on the command line, it reads the part fine.

Questions are, where is the source code for i2cdump and how can my user space application access the same driver, and most importantly, where can I find that documentation gold mine so I don’t have to ask the same question when I move on to the SPI bus next.

Thanks!
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Problem Running Nios II Design Standalone

January 28, 2014, 2:41 pm
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Normally I use HDL for everything, but I’m trying to move into soft processor and SoC design. I created a Quartus/Qsys project to run the Nios II Binary Count example code project on a DE0-Nano development board. I picked the Nios II economy core since it’s free.

Everything worked from inside Eclipse (except for an occasional mystery error about timestamps not matching). I was able to run the Binary Count project and see the LEDs iterate endlessly through a counting pattern on the DE0-Nano hardware. At that point, I followed Altera’s instructions for generating a memory initialization file from Eclipse and adding it to the FPGA project.

My goal was to have the board power up running the led_count code, so I added the memory init file, built the FPGA project to get an updated .sof, converted the .sof to a .jic, and programmed the .jic to flash on the DE0-Nano board.

Now, when I power on the DE0-Nano I see the LEDs count. Success! Well, not quite. It only runs for about 1 minute before freezing. The LEDs count from 0-255, then 0-98. At that point they stop changing forever. It is 100% repeatable and always stops on the same value of 98.

When running from Eclipse, the program never halts like this. I’m struggling to come up with a reason the program runs seemingly forever from Eclipse, but only lasts a minute when running standalone. Am I missing something obvious?

For a reference, here is a screenshot of the Qsys design.
Qsys_system.jpg
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Onchip memory

January 28, 2014, 6:44 pm
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Altera Cyclone II DSP development board (EP2C70F672C6).We r doing image processing.
we have seen test pattern generation, which is available on this website.
It is working fine but we r unable to understood the procedure specially onchip memory.
It is shown that onchip memory could be increase from 4k to 20k.
Please explain how they have done this expt., without ddr2 RAM.
Tell us if it is possible to increase on chip memory and tell us if it is possible that we could use onchip memory for display of image without use of ddr2 sram.
so that we can import image from computer and display on vga monitor.


Attached Files
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Strange error from aocl diagnostic

January 28, 2014, 8:18 pm
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I am trying to use OpenCL code with a Terasic DE5Net FPGA. The code compiles but the host program has errors, When I was trying to troubleshoot I went ahead and used command

Code:
aocl diagnostic
which returned the following error:
Code:
aocl diagnostic: Running diagnostic from /home/aws4y/altera/13.1/hld/board/terasic/de5net/linux64/bin
running diagnostic for : acl0
FPGA is in user mode. Enabling bridges
Using platform: Altera SDK for OpenCL
Failed clGetDeviceIDs.
Error code: -1
aocl diagnostic: failed.
I do not understand how clGetDeviceIDs fails, I don't think there is a problem with the board but maybe with the configuration. I am trying to use the PCI Express bus with the card is that incorrect? Could it be a configration issue with CentOS or the Altera OpenCL sdk?

-Aaron
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which cyclone?

January 28, 2014, 8:41 pm
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I am new to Altera devices. I am trying to decide between Cyclone 3, 4 and 5. But still confused.
My main requirements are -

Number of IOs: Same package/footprint should be available with higher IOs
Power consumption - not a big deal
Long device life: at least 5 yrs before being obsoleted. Preferably 10 yrs.
IOs operating at 3.3V
Application is general purpose logic, no high speed serial stuff.

I am inclined toward Cyclone 5, since it's the newest in the Cyclone family.
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Nios II basic

January 28, 2014, 9:44 pm
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Hi,
I am a beginner .I am using Nios II development kit stratix II Ep2s60f672c3n. In the flash memory of board contains nios file.while power on file transfer to fpga...

It means can I directly program onto nios now??? that is using eclipse.
or I need to develop nios and programmed onto fpga using sopc builder?

please reply
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to start nios on nios development kit

January 28, 2014, 9:58 pm
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Hi,

To start nios II IDE ,tool>sopc builder

but in quartus II 13.0 and later version in tool, no sopc builder option available.so which option to click to start nios II IDE.

Please reply

Thank you
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Size of C file running using NIOS II ON CHIP RAM

January 28, 2014, 11:15 pm
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How to figure out how much amount of space is being occupied by the C.c file which is used to to run as an NIOS II hardware ??

For example in the file http://www.altera.com/literature/hb/...mi_tut_qdr.pdf
consider I am running the DDR_TEST.c file on the NIOS II processor. What will the memory occupied int he ON CHIP RAM???
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Problem with design project for Quartus (device - MAX II)

January 29, 2014, 6:48 am
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Hellow.

I want develop some project on EPM570GM100I5N (MAX II family), but I can't find this device (and other G MAX II devices ) in Quartus II 12.1sp1 Web Edition (64-Bit). How can I solve this problem (I should change device (for example EPM570ZM100I8N) or I should download some addition for Quartus)?
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Hex to Mif file converter for LM32 Hex files

January 29, 2014, 10:57 am
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I have ported the LatticeMico32 to an Altera Cyclone. I have a 8K x 32 memory but the hex file I have has 4 words per line and I get the following line while trying to compile in quartus II 13.1


Warning (113009): Data at line (1) of memory initialization file "yo.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.

The program used to generate the hex file, lm32-objcopy.exe does not have an option to make less than 4 32-bit words per line.
Does altera have any tools that could convert the files to the right format or mif file? I tried the elf2mif program but it doesn't seem to be working on cygwin nor my elf files..is it only for NIOS elf files?

Salman
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Altera EP1C12Q240C8 model for Multisim database or Altium Designer?

January 29, 2014, 1:09 pm
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I am drawing schematic as EP1C12Q240C8, But cant find out this chip in Multisim or Altium Designer database.
Where can I find it? or I have to design by myself? :confused::confused::confused:

thanks!
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Quartus II Supported Devices by release version

January 29, 2014, 1:29 pm
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Hi,

I have been looking through the Quartus release notes to find out the highest revision of Quartus II that supports a particular CPLD (Max EPM7128S). The release notes seem to list the new devices supported in that release, but not the products no longer supported.

Can someone let me know how I can find this info please?

regards
Dave
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Terasic DE4 - SDRAM 4GB IP sample

January 29, 2014, 1:43 pm
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Hello there,

I have a Stratix board Terasic DE4 and want to run SDRAM 4GB that I have. But I couldn't find any information, or sample to use SDRAM in Qsys or SOPC. I have DSL 4GB brand name. Do I need to buy IP for this SDRAM?

Best,
Sean
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