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Are FPGA's getting too complex?

January 29, 2014, 2:13 pm
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Hello, I would like to know how people think about my comments concerning the increasing complexity with today's FPGA's? This will date me but I'm just now learning TimeQuest and admit that it is a very powerful tool but it does take some training to get proficient. Many of my co-workers have stayed with Quartus 9.1 for that reason. With the recent launch of the embedded hard-core processor came another tool that one must pick up and learn, SoC Embedded Design Suite, Altera SDK for OpenCL, SOPC Builder, Qsys. With all these new tools that one must struggle to learn I begin to think that maybe FPGA's are not worth the trouble. Maybe the tools will get too complex and costly in terms of labor that designers will opt for something else such as the new DSP's that have just about every peripheral interface one might need and multiple cores running a 1GHz and higher and all running under one IDE. I am anxious about the Stratix 10 but from what I see so far with the complexity of the tools and the large megafunctions that require the NIOS processor or embedded Linux I'm taking a closer look at other options.

What are other thinking about the complexity with the newer FPGA's and where Altera is going?

Thanks,
joe
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ALU in VHDL newbi having some major issues

January 29, 2014, 4:13 pm
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Hi guys, I need to serious help over here. I need to code an ALU that can perform different function base on the op code, add, subtract, logical shift left and right.

namely these:
opCodeInstructions.jpg

Now my main problem right now is.. i have no clue how to implement the condition statements correctly so that I can pick and choose what operation I need to perform. I think i managed to code an full adder/subtract r.. but I dont know how to implement it under a condition .. keep getting compile time errors if i try anything... I want to keep everything in one file.. i dont want to use packages.. Can some one please help me!? this is what I have so far.. it compiles as is, but the comments will tell you my struggles..

Code:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
    PORT ( a, b, cin : IN STD_LOGIC ;
            s, cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
    s <= a XOR b XOR cin ;
    Cout <= (a AND b) OR (cin AND a) OR (cin AND b) ;
END LogicFunc ;






LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--USE work.fulladd package.all ;


ENTITY alu IS
--GENERIC ( n : INTEGER := 32 );
PORT(
    a        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
    b        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
    cin  : IN  STD_LOGIC;
    S    : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --sum
    cout    : OUT STD_LOGIC;
    op    : IN  STD_LOGIC_VECTOR( 2 DOWNTO 0);
    zero    : OUT STD_LOGIC);
END ENTITY alu;   


--ARCHITECTURE description OF alu IS BEGIN
-- You fill in what goes here!!!! END description;




--process(all)
--begin   
       
              architecture LogicFunc of alu is
                        signal c : std_logic_vector(0 to 30); -- internal carry signals
                        begin 
                        a0: entity WORK.fulladd port map(a(0), b(0), cin, S(0), c(0));
                        stage: for I in 1 to 30 generate
                            as: entity WORK.fulladd port map(a(I), b(I), c(I-1) , S(I), c(I));
                        end generate stage;
                        a31: entity WORK.fulladd port map(a(31), b(31), c(30) , S(31), cout);
                    end architecture LogicFunc; 
     
        --      architecture LogicFunc of alu is
            --            signal c : std_logic_vector(0 to 30); -- internal carry signals
            --            begin 
            --            a0: entity WORK.fulladd port map(a(0), b(0), cin, S(0), c(0));
            --            stage: for I in 1 to 30 generate
            --                as: entity WORK.fulladd port map(a(I), b(I), c(I-1) , S(I), c(I));
            --            end generate stage;
            --            a31: entity WORK.fulladd port map(a(31), b(31), c(30) , S(31), cout);
            --        end architecture LogicFunc; 
               
 
   
--end process;   




                           
                               
--END description;                               


                           
                           
--ARCHITECTURE Structure OF alu IS
--    SIGNAL C : STD_LOGIC_VECTOR(0 TO n) ;
--    COMPONENT fulladd
--        PORT ( Cin, x, y : IN  STD_LOGIC ;
--                    s, Cout : OUT STD_LOGIC ) ;
--    END COMPONENT ;




--BEGIN
--    C(0) <= Cin ;
--    Generate_label:
--    FOR i IN 0 TO n−1 GENERATE
--        stage: fulladd PORT MAP ( C(i), a(i), b(i), result(i), C(i+1)) ;
--    END GENERATE;
--    Cout <= C(32) ;
--END Structure;


--stage0: fulladd PORT MAP ( Cin, a(0), b(0), S(0), C(1) ) ;
--stage1: fulladd PORT MAP ( C(1), a(1), b(1), S(1), C(2) ) ;
--stage3: fulladd PORT MAP ( C(2), a(2), b(2), S(2), C(3) ) ;
--stage4: fulladd PORT MAP ( C(3), a(3), b(3), S(3), C(4) ) ;
--stage5: fulladd PORT MAP ( C(4), a(4), b(4), S(4), C(5) ) ;
--stage6: fulladd PORT MAP ( C(5), a(5), b(5), S(5), C(6) ) ;
--stage7: fulladd PORT MAP ( C(6), a(6), b(6), S(6), C(7) ) ;
--stage8: fulladd PORT MAP ( C(7), a(7), b(7), S(7), C(8) ) ;
--stage9: fulladd PORT MAP ( C(8), a(8), b(8), S(8), C(9) ) ;
--stage10: fulladd PORT MAP ( C(9), a(9), b(9), S(9), C(10) ) ;
--stage11: fulladd PORT MAP ( C(10), a(10), b(10), S(10), C(11) ) ;
--stage12: fulladd PORT MAP ( C(11), a(11), b(11), S(11), C(12) ) ;
--stage13: fulladd PORT MAP ( C(12), a(12), b(12), S(12), C(13) ) ;
--stage14: fulladd PORT MAP ( C(13), a(13), b(13), S(13), C(14) ) ;
--stage15: fulladd PORT MAP ( C(14), a(14), b(14), S(14), C(15) ) ;
--stage16: fulladd PORT MAP ( C(15), a(15), b(15), S(15), C(16) ) ;
--stage17: fulladd PORT MAP ( C(16), a(16), b(16), S(16), C(17) ) ;
--stage18: fulladd PORT MAP ( C(17), a(17), b(17), S(17), C(18) ) ;
--stage19: fulladd PORT MAP ( C(18), a(18), b(18), S(18), C(19) ) ;
--stage20: fulladd PORT MAP ( C(19), a(19), b(19), S(19), C(20) ) ;
--stage21: fulladd PORT MAP ( C(20), a(20), b(20), S(20), C(21) ) ;
--stage22: fulladd PORT MAP ( C(21), a(21), b(21), S(21), C(22) ) ;
--stage23: fulladd PORT MAP ( C(22), a(22), b(22), S(22), C(23) ) ;
--stage24: fulladd PORT MAP ( C(23), a(23), b(23), S(23), C(24) ) ;
--stage25: fulladd PORT MAP ( C(24), a(24), b(24), S(24), C(25) ) ;
--stage26: fulladd PORT MAP ( C(25), a(25), b(25), S(25), C(26) ) ;
--stage27: fulladd PORT MAP ( C(26), a(26), b(26), S(26), C(27) ) ;
--stage28: fulladd PORT MAP ( C(27), a(27), b(27), S(27), C(28) ) ;
--stage29: fulladd PORT MAP ( C(28), a(28), b(28), S(28), C(29) ) ;
--stage30: fulladd PORT MAP ( C(29), a(29), b(29), S(29), C(30) ) ;
--stage31: fulladd PORT MAP ( C(30), a(30), b(30), S(30), C(31) ) ;
--stage32: fulladd PORT MAP ( C(31), a(31), b(31), S(31), cout ) ;
--END Structure ;

please help me!

oh and I can't use add or subtract operator, must be using logic gates.
Attached Images
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Accessing EEPROM on I2C Bus 0 - Altera Arrow SoC kit

January 29, 2014, 8:21 pm
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Hi experts,
On detecting the I2C devices on I2C Bus 0 for Altera SoCkit by using i2cdetect command in linaro filesystem,

$ i2cdetect -y 0
Error: Can't use SMBus Quick Write command on this bus

But i was then able to detect EEPROM and LCD on I2C Bus 0 using the command as follows,

$ i2cdetect -r 0
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0 using read byte commands.
I will probe address range 0x03-0x77.
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- UU -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

But when i try to read/write to EEPROM on I2C0 using I2C SMBUS read in code / using i2cget, im getting error: read failed.

So on trying to access using /sys/bus/i2c/devices/0-0051, i face a time out issue as follows,
cat: /sys/bus/i2c/devices/0-0051/eeprom: Connection timed out

And its I2C debug messages are,
i2c i2c-0: master_xfer[0] W, addr=0x51, len=2
i2c i2c-0: master_xfer[1] R, addr=0x51, len=128
i2c_designware ffc04000.i2c: i2c_dw_xfer: msgs: 2
i2c_designware ffc04000.i2c: i2c_dw_isr: Synopsys DesignWare I2C adapter enabled= 0x1 stat=0x10
i2c_designware ffc04000.i2c: i2c_dw_isr: Synopsys DesignWare I2C adapter enabled= 0x1 stat=0x110
i2c_designware ffc04000.i2c: i2c_dw_isr: Synopsys DesignWare I2C adapter enabled= 0x1 stat=0x150
i2c_designware ffc04000.i2c: i2c_dw_handle_tx_abort: slave address not acknowledged (7bit mode)

Any idea/help on accessing the EEPROM on I2C0 will be much more appreciated.

Thanks,
Dhiv
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EPM7064s INPUT/OE/GCLK pins connection while using ISP(JTAG)

January 30, 2014, 4:01 am
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Hello,

At the moment I'm a student at Avans Hogeschool in the Netherlands. I want to use the EPM7064s CPLD for a project.

I would like to program it with JTAG. I only have a question about how I need to connect the 4 dedicated INPUT / OE / GCLK / GCLRn pins when I want to use the ISP function with JTAG. Pin 1, 2, 43 and 44 of the EPM7064s, 44-pin PLCC package.

For example, do I have to pull those pins up with a resistor?

Thanks,

Michiel
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clock division in verilog

January 30, 2014, 4:46 am
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I'd like some help to understand why this code didn't work.
----------------------------------------------
module emissao2(
clk,


enable_in,
over_temp_in,
MSB_in,
LSB_in,


enable_led,
over_temp_led,
MSB_led,
LSB_led,


enable_out,
over_temp_out,
MSB_out,
LSB_out,


ctrl_p_1,
ctrl_n_1,
ctrl_p_2,
ctrl_n_2,
ctrl_p_3,
ctrl_n_3,
ctrl_p_4,
ctrl_n_4);




//---Input Ports---
input clk;
input enable_in;
input over_temp_in;
input MSB_in;
input LSB_in;


//---Output Ports---
output enable_led;
output over_temp_led;
output MSB_led;
output LSB_led;


output enable_out;
output over_temp_out;
output MSB_out;
output LSB_out;


output ctrl_p_1;
output ctrl_n_1;
output ctrl_p_2;
output ctrl_n_2;
output ctrl_p_3;
output ctrl_n_3;
output ctrl_p_4;
output ctrl_n_4;


//---Input Ports Data Type---
wire clk;
wire enable_in;
wire over_temp_in;
wire MSB_in;
wire LSB_in;


//---Output Ports Data Type---
reg enable_led;
reg over_temp_led;
reg MSB_led;
reg LSB_led;


reg enable_out;
reg over_temp_out;
reg MSB_out;
reg LSB_out;


reg ctrl_p_1;
reg ctrl_n_1;
reg ctrl_p_2;
reg ctrl_n_2;
reg ctrl_p_3;
reg ctrl_n_3;
reg ctrl_p_4;
reg ctrl_n_4;


reg [3:0]count;


initial begin
count = 4'd0;
ctrl_p_1 = 1'b0;
end


always @(posedge clk)
begin
if(count==4'd10)
begin
count<=3'd0;
ctrl_p_1 <= ~ctrl_p_1;
end
else
begin
count<=count+1;
end
end


endmodule
----------------------------
It compile but does not work. I made the assignments correctly, and i will use all this ports, this is just a inicial code just to see if works.
I'm using Quartus II 13.0, to program Altera DE2 (EP2C35F672C)
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hardware implementation of STFT ?

January 30, 2014, 5:20 am
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Hello everybody

I'm working with the short time Fourier transform (STFT), I would like to implement and show the results on a screen using VGA port, but I do not have idea how to do it.

I would appreciate your help...


thanks.
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Information about cyclonev_termination_logic_encrypted, cyclonev_dll_encrypted

January 30, 2014, 5:30 am
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Hello,

I try to simulate a DDR3 Uniphy design with ModelSim . I use Mentor Graphics Hdl Author tool to manage my libraries and launch Modelsim from this tool.
My design uses some of altera libraries, so that I mapped these compiled libraries accordingly. After I start ModelSim simulation ends with the following errors:
..../quartus/eda/sim_lib/cyclonev_atoms.v(3714): Instantiation of 'cyclonev_termination_encrypted' failed. The design unit was not found.
I get the same message for the title files as well. Please note that my version of Quartus is 13.1 web edition and some features might not be available. But can you confirm these 3 files are to be found only in the Quartus Subscription edition , or should I look for the root of the problem somewhere else?

Many thanks,
Florin
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Verify failed between adress ... on very simple design

January 30, 2014, 6:10 am
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Hi everyone,

i know this subject has been discussed a lot of times, but i don't find any solution for my case.
I 'm working on a DE2 115 board trying to get a TCP stack on uCos.
As usual, i do my SoC with a nios 2 and so on...
But when i tried to download the .elf to the system i got this great message that tells me "failed to download .elf" and a "verify failed between address x80000 and ...".nice_message.jpg This address range corresponds to my main memory.

So, i did a very simple design with a nios2, jtag uart and mem of 65536 Bytes, just to see the behavior, and guess what? it doesn't work neither and tells me the same message.

I did a project 6 months ago with 11.1 version of Quartus and i never encountered this problem.
Since i installed the new 13.1 version a week ago, i got this message on all my old designs.

Is it possible that 13.1 hates me? I never cheated it, or maybe one time. This was a night, MicroSemi just told me how beautiful i was, and i... No, i just don't want to remember.

If someone has the solution, i take it. Thank you.
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MOdelSim doesn't support multiple modules in single .v file?

January 30, 2014, 12:32 pm
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I get an error trying to load design, when using single .v file with all modules in it, if I have individual files for each module it happy, does that sound right? any way around that?
thanks
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INIT_CONFIGURATION JAM action with Serial FlashLoader (SFL)

January 30, 2014, 6:51 am
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I would like to "initiate configuration after programming" using the JAM player with the following setup: I have a Cyclone V FPGA configured with an Enhanced Serial FlashLoader (SFL) and an attached EPCS device. I use the JAM player (quartus_jli) to program the serial flash over JTAG. After which, I would like to issue a JAM player command to initiate configuration.

Apparently there is a way to do this with the Parallel FlashLoader (http://www.altera.com/support/kdb/so...12011_696.html).

Unfortunately, the INIT_CONFIGURATION action does not appear to be a part of the Quartus II-generated JAM file. Is there an option to have Quartus II include the the INIT_CONFIGURATION?

Is there another way to initiate configuration after programming using a command-line utility?
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Using CPLDs as a dedicated DDC

January 30, 2014, 3:30 pm
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Hi,

The have an ADC sampling at 37.4MSps and I want to fed this data into a DSP for real-time baseband processing. However, I need an interface between the ADC and DSP to digitally down converter the bandwidth of interest (6MHz at Fs/4 = 9.35MHz) to baseband, so the DSP processing load is reduced. I'll use a NCO generating a signal at Fs/4 - 9.35MHz, also generating I and Q. This shouldn't need too many resources.

I'm looking for a low cost solution (rather than using FPGA or ICs) and I am wondering if a DDC can easily be implemented by a CPLD?
There doesn't seem to be many resources online for this.

Kindest regards,
Les.
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Fatal: Error occurred in protected context

January 30, 2014, 6:43 pm
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# ** Fatal: Error occurred in protected context.
# Time: 0 ps Iteration: 0 Protected: /fusiontestdebugtb/u_DebugApp/\nios2_qsys|enet_pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL\/inst/<protected> File: nofile
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design

I get the error-message given above when I try to load the my design (for altera arriaV FPGA family) in altera-modelsim.

My design includes couple of megafunctions, nios2 processor. I have included relevant files for the megafunctions, arriaV atom file. Please help me with the error above

-Karthik.
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IIR filter implementation in verilog

January 30, 2014, 10:48 pm
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does anyone have the idea how to get rid of extra bits that comes in IIR filter due to feedback?each time the feedback occurs the inputs bits gets changed and so is the case with the output bits?I just need the concept of setting this bit width in IIR filter input ant output sides.
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Cyclone III: can't achieve specified port rate

January 31, 2014, 2:52 am
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Hello,
I have problems to meet timing requirements, getting "minimum pulse width"-violations with "port rate"-type.
Design consists of clock input (50MHz, pin_t9), PLL and clock output(100MHz, pin_l1). Device is EP3C25U256C8. Current strength @8mA, slew rate 2.


Timequest reports "minimum pulse width"-violations at the clock output with -3.481 slack.
If I understand it correctly, the output toggle rate is specified up to 200MHz with this settings. Any suggestions what the problem is?


Best regards
Jaroslav
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WHEN with STD_LOGIC_VECTOR gives error for ''00'' but not for '0'&'0'

January 31, 2014, 3:26 am
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Well, I'm completely new VHDL and Quartus but I came across something which I don't understand while doing an assignment today. I'm writing a 2 bit multiplexer but I included only two signals here to illustrate the issue:

Code:
library ieee;
use ieee.std_logic_1164.all;

entity mux_test is
    port(
    a,b  : in std_logic;
    s    : in std_logic_vector(1 downto 0);
    x      : out std_logic );

end mux_test;
architecture behaviour of mux_test is
begin
   
    x <= a when s =''00'' else
          b;

end behaviour;
Compiling this doesn't work, I get the error message:
Error (10500): VHDL syntax error at mux_test.vhd(16) near text "'"; expecting "(", or an identifier, or unary operator

However, if instead of when s=''00'' I write when s='0'&'0' it compiles fine and I can write a multiplexor using this notation instead. However, I don't see why the standard way of writing it doesn't work; it's used everywhere on the internet I have looked and in textbooks. Is there something I'm missing or some bug in the program? I'm using Quartus II 13.0 with Linux Mint 13 Maya.
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Programming an EPCS4 using JTAG and Quartus II + SFL

January 31, 2014, 5:08 am
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Hello,

I am having problems trying to program an EPCS4 attached to a Clyclone IV EP4CE6F17I7 with the JTAG interface (and a USB-Blaster). The EP4CE6 is in a JTAG chain with an Atmel AT91SAM9261 Microcontroller, as follows:
TDI -> AT91SAM9261 -> EP4CE6 -> TDO

The EPCS4 flash device is attached to the EP4CE6 with AS configuration scheme (MSEL0=0, MSEL1=1, MSEL2=0).

Programming the EP4CE6 itself works fine, but not the flash device. I am using the method described in AN370, i.e.:
1) Convert .sof file to .jic file (p 11)
2) Program the flash using Quartus II programmer and .jic file (p 17)

I get the messages:
Info (209060): Started Programmer operation at Fri Jan 31 13:25:55 2014
Info (209016): Configuring device index 2
Info (209017): Device 2 contains JTAG ID code 0x020F10DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Error (209025): Can't recognize silicon ID for device 2
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Fri Jan 31 13:25:56 2014

Testing the JTAG chain using the JTAG Chain Debugger gives this:
!Info: JTAG chain connection is good. Detected 2 device(s)
!Info: Device 1: AT91SAM9261 (USERCODE: - )
!Info: Device 2: EP3C(10|5)/EP4CE(10|6) (USERCODE: 0xFFFFFFFF)


Note: I am using Quartus II 12.0 SP2.16

Thank you for your help,

Regards,

Alex
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Sleeping DDR3 controler

January 31, 2014, 8:51 am
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Hi,
i am using the DDR3 uniphy controler (QII V13.1) on a Stratix4GX 530 (evaluation board from Altera) and i am a little bit surprised that after a short period of high activity then signal "avl_ready" is deasserted for a few (4 to 6) µs though there is absolutely no activity on memory bus!
this is not very convenient to achieve performances goals.
Is this a normal behavior or do i miss something on the IP configuration?
Thanks to anyone abble to answer.
Jean Rene
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Programming update fail

January 31, 2014, 8:56 am
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I'm using QuartusII 13.1 . I change some constant variables connected directly to the outputs but it seems that the program entering the FPGA does not change since the "check sum" does not change in the programmer. Is there something wrong with the installed Quartus or am i missing something?

Thanks
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altclkctr ip error when i supply two clocks (no PLL) that i'm trying to mux between

January 31, 2014, 11:01 am
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Hi All,

really appreciate any kind of help regarding this issue,

the error i receive is:

Error (176375): Can't place Clock Control Block bc_gpiopld:karkom_bc_gpiopld|pch_bios_to_7seg_espi _lpc_if_unit:espi_lpc_unit|clkmux:clkmux_inst|clkm ux_altclkctrl_7ji:clkmux_altclkctrl_7ji_component| clkctrl1 in location <nothing> -- location conflicts with source nodes of inclk ports
Info (176376): Placed node C_PCH_GPP_A_10_CLKOUT_LPC_1_RR~input in location PIN J28 (CLK5, DIFFCLK_2n)
Info (176377): Clock Control Block can be placed at location CLKCTRL_G7
Info (176377): Clock Control Block can be placed at location CLKCTRL_G6
Info (176376): Placed node C_CLK_HKSCLK_FPGA~input in location PIN J1 (CLK1, DIFFCLK_0n)
Info (176377): Clock Control Block can be placed at location CLKCTRL_G2
Info (176377): Clock Control Block can be placed at location CLKCTRL_G1

i don't understand the error message and the help by altera:

CAUSE: The Fitter cannot place the specified Clock Control Block due to conflicts with the locations of the nodes that feed the inclk ports of the Clock Control Block. This error can occur when the location of the inclk port source nodes prevent the nodes from being able to feed a Clock Control Block. Click the + icon to display details on the location of the source nodes for the inclk ports of the Clock Control Block.
ACTION: Assign the Clock Control Block or the source nodes of the inclk ports so that the source nodes can feed the inclk ports of the Clock Control Block.


i was under the impression that i supply two clocks and select net again both none PLL

the device i use is Cyclone IV E: EP4CE30F29C8 on quartus version 13.1

Thanks,

EA
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Simulation Freezing

January 31, 2014, 11:33 am
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I'm trying to simulate a code written in Verilog in Quartus using ModelSim but whenever it wants to simulate the code I see the whole software freezing. I tried reinstalling the software but it did not help. Does anyone know what could be the cause of this issue?

Thanks!
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