Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Stratix IV design example

February 18, 2014, 11:27 pm
$
0
0
Hi,

I look to use a DSP builder to implement a filter FIR on my board Sratix IV EP4SGX230KF40C2 through SOPC tools. Can you help me to get a sample design to start from it.

Thank you
↧
Search

Arria V Transceivers

February 19, 2014, 12:56 am
$
0
0
Hello,


I am trying to use arria V GX transceivers but I am PCB designer and I feel a little lost in this field. I want to transmit a 960 Mbps data rate to a main board from a daughter board. I can use only one channel to do this (one tx channel in the daughter board and one rx channel in the main board) and I would like to know what resources I will need.


The daughter board has a DDR2 memory with a image which I have to send to the Main board by means of a data flow, this flow has to have the recovery clock included, I think this is possible using 8b/10b codification. My question is basically if, besides the tx channel and the rx channel, I need a input transceiver clk (generated by a external oscillator of 120MHz (8bits*120MHz=960Mbps)) in each FPGA, in the daughter board to generate the data flow and in the main board to recovery it.


Thanks in advance.
↧
↧

modelsim, transcript and input test signal

February 19, 2014, 2:13 am
$
0
0
Hello guys,

I have some issues when trying to set-up the input signal of a vhdl design in transcript.

From what I have undestand, supposing that my input signal is
Code:
/d
, if I want the signal to have a change of 10 every 100 ns I should write :

Code:
vsim> force -deposit /d 10#0, 10#10 100, 10#30 100, 10#40 100
By the way, when I run the model (run 500) I see that the
Code:
/d
waveform has a value of 0 at 0 ns, changes to 40 at 100 ns and then remains at 40.

What am I missing ??

Thank you for any suggestions.

Have a nice day.
↧

Custom library in Altera

February 19, 2014, 3:48 am
$
0
0
Hi all,

I have a custom library of components which I will be using on my projects on demand. I have put these components in a directory called Elements. In each of the entities and packages in this directory I have put the directive -- synthesis library Elements at the top of each file.I have also wrote a package that calls these entities as a component as well as some custom functions. I have called this Elements_Package

In the VHDL units that will be using these entities I have used the directive library Elements and the use clause use Elements.Elements_Package.all. I have also included the path in the Tools-Options-Libraries-Global libraries.

When running the synthesis tool I am getting this error "Error (10481): VHDL Use Clause error at Design.vhd: design library "Elements" does not contain primary unit "Elements_Package"" and "Error (10800): VHDL error at Design.vhd(7): selected name in use clause is not an expanded name"

I am using Quartus 11.0SP1

What am I doing wrong?

Thanks,

jozamm
↧

pwm generation

February 19, 2014, 4:32 am
$
0
0
Hi,

I would like to know is there any possibility to use always inside for loop??

please anybody explain the errors associated with my code both logical and coding syntax issues

ThankYOU
Attached Files
↧
↧

Depicting "hello world' on Cyclone III's seven segment display with NiosII processor

February 19, 2014, 5:04 am
$
0
0
Hello people,
i am new to Fpga design and i just want to write a simple 'hello world' on the seven segment display of Cyclone III using a NiosII processor.
I am using an exaple design of Nios II as it is on altera's site for download.
'hello world' runs in the Nios command shell but not at the seven segment display.Do i need some drivers to do it?
Anyone who can help me?\
Thanx a lot in advance!
↧

SockIt System Console in Q-II v13.1

February 19, 2014, 5:44 am
$
0
0
Hi,

I'm just posting a problem that I found in trying to run the Arrow SoC Hardware Lab on the Sockit board in the hope of helping others avoid it.

In Module 6: System Console, the test_one.tcl script works fine when run under Q-II v13.0, but fails under v13.1.

I've traced this down to the address format in the tcl scripts. For example in test_one.tcl you may find a line:

master_write_8 $jtag_master 0x1_0040 $val

v13.1 of Q-II doesn't like the underscore in the address, so 0x1_0040 needs to be changed to 0x10040.

All of the underscores in the addresses in the scripts appear to need to be removed.

I hope this helps others.
Cheers
AL
↧

ModelSim Error question

February 19, 2014, 5:51 am
$
0
0
Hi,
When I try to Run my simulation I keep getting the following error immediately.
Any explanation would be appreciated.

Thanks!
Larry

ERROR MSG
# Internal Error: In tclprim_ApplyStimulus for /motor/reset_low_sync "** Error: (vsim-3462) Value/time pairs must be listed in increasing time order.
↧
Search

OpenCL licensing

February 19, 2014, 6:31 am
$
0
0
Hi,

We are looking into evaluating Alter's OpenCL support currently.

However, once we complete our design based on OpenCL, I wonder:

- Will we be able to run our code on custom boards integrated into our products using a CycloneV SoC?
In this case the aoc compiler can't know about the board used.

- Is it possible to combine OpenCL kernels with "normal" VHDL code in a single image.
While we prefer to write our compute kernels with OpenCL, low-level interfaces to external devices would require VHDL.

- What licensing options are available? What additional costs will arise from the fact we are using OpenCL instead of VHDL?
For now it seems the license is bound to the fpga-board, right?

Thank you in advance, Clemens
↧
↧

Error while trying to program EPCS flash in indirect SFL mode

February 19, 2014, 10:46 am
$
0
0
(editing my previous thread for an update and save make the thread becomes blank, so I'm re-posting it as a new thread here)

Hi,

On my new CoreEP4CE10 board, I'm able to upload designs successfully in FPGA
Ram using JTAG, but I'm unable to program EPCS Flash using JTAG Indirect SFL
mode.
Since this board doesn't have an AS connector, I have no other choice to
program using SFL, so I decided to try at command-line, but I got same
problem :

We can see below that SFLoader is actually succesfully loaded, but then the
JTAG hang and the EPCS is not detected.
Question : Are all boards using same FPGA are compatible with those SFL
"Factory default enhanced SFL image" provided ? Should I try to make my own
loader using SFL Megafunctions ?

Info: ************************************************** *****************
Info: Running Quartus II 64-Bit Programmer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Feb 19 12:11:02 2014
Info: Command: quartus_pgm -m JTAG -o pi;output_files/blinker.jic
Info (213045): Using programming cable "USB-Blaster(Altera) [1-1.3]"
Info (213011): Using programming file output_files/blinker.jic with checksum
0x1A5AF94D for device EP4CE10@1
Info (209060): Started Programmer operation at Wed Feb 19 12:11:03 2014
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F10DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Error (209037): JTAG Server can't access selected programming hardware
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Wed Feb 19 12:11:26 2014
Error: Quartus II 64-Bit Programmer was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 286 megabytes
Error: Processing ended: Wed Feb 19 12:11:26 2014
Error: Elapsed time: 00:00:24
Error: Total CPU time (on all processors): 00:00:00

UPDATE :

Following instruction of the Troubleshooting page
(http://www.altera.com/cgi-bin/ts.pl?...uration&hi=2-8), I've manually
uploaded the SFL into the FPGA, then I've performed an antodetect again, and
I'm unable to see the EPCS, I'm only seeing the FPGA itself. Doing the same
at the command-line "jtagconfig" only shows the FPGA where I presume the
EPCS should also appear, but it doesn't ... I've check power supply
voltages, they look fine ... Is that mean my USB Blaster is defective (but
why I'm able to upload FPGA properly) ?
↧

Color Space Converter not generated corectly

February 19, 2014, 11:05 am
$
0
0
Hi all, I try to use the CSC IP for converting my Video Stream from RGB to YCrCb. It use the MegaWizard to generate a CSC VHDL IP Module suiting my needs. But the generated file csc.vhd has a syntax error. This is very strange, but not the real problem. when I start the synthesis following errors happen.
Code:
Info (12128): Elaborating entity "csc_in" for hierarchy "csc_in:sRGB_YCrCb_1"
Warning (277001): IP Generator Warning: This module has no ports or interfaces
Info (12021): Found 2 design units, including 1 entities, in source file db/csc_in_gn.vhd
Info (12022): Found design unit 1: csc_in_GN-rtl
Info (12023): Found entity 1: csc_in_GN
Info (12128): Elaborating entity "csc_in_GN" for hierarchy "csc_in:sRGB_YCrCb_1|csc_in_GN:auto_inst"
Warning (12158): Entity "csc_in_GN" contains only dangling pins

....
Error (12002): Port "clock" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "din_data" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "din_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "din_ready" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "din_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "din_valid" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "dout_data" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "dout_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "dout_ready" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "dout_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "dout_valid" does not exist in macrofunction "sRGB_YCrCb_1"
Error (12002): Port "reset" does not exist in macrofunction "sRGB_YCrCb_1"
They are correct, because the "db/csc_in_gn.vhd" file has a entity with no ports, but why?
Did someone have the same problem? I use Quartus 13.1 with update 2 installed and a Cyclone 5 SoC. ( The error also happened before the update)

Regards,
Chris
↧

Clearing the read and write pointer; DCFIFO

February 19, 2014, 4:06 pm
$
0
0
I need to transmit data from the write domain (at 84Mhz) to the read domain(at 38Mhz) and I'm using "DCFIFO" to buffer.

I learn't that the DCFIFO is not a circular FIFO. And due to this I will need very deep fifo for my application. I set "aclr" signal to clear the write pointer but then it resets the read pointer too.
When this happens, I lose the data which I haven't read yet.

My question is:
Is there a way to clear only the write pointer and ensure the read pointer keeps reading from the same position?
↧

Error on simulation: Quartus 13.1 + Qsim + Modelsim

February 19, 2014, 4:07 pm
$
0
0
Hello,

I am trying to simulate using vwf files in Quartus 13.1 + Qsim. I create the vector waveform file and then I try to
run a functional simulation, but I got the error below

# ** Error: (vsim-3170) Could not find 'work.mydesign_vlg_vec_tst'.

#

# Error loading design

Error loading design



Error.


I believe this vlg is related to verilog (my hardware descriptions are in vhdl). There is only one file
named mydesign.vhd in my project. Any ideas of what is the problem?

Thank you all
↧
↧

How to solve nSTATUS can't go high

February 19, 2014, 11:10 pm
$
0
0
I have made a FPGA board using Cyclone V SOC 5CSXFC6D6F; The HPS is running, the Quartus Programmer can detect the HPS(SOC part), but the FPGA part can't be detect via JTAG; and I've found the nSTATUS can't go high after power up, but generate a pulse about 4.3kHz.
↧

DDR2 MT47H16M16BG Signal Integrity Analysis

February 20, 2014, 2:23 am
$
0
0
Hi I am using Cyclone IV FPGA Development board and would like to do Signal Integrity analysis for the same.

Can anyone give IBIS models for DDR2 MT47H16M16BG from Micron. I am not even able to locate this IC on website micron.com

I hope that this device is not obsolete.

Thanks
↧
Search

Trouble setting signal value

February 20, 2014, 2:54 am
$
0
0
I have made this program as part of an assignment where I'm supposed to design a one bit voter, for micro controllers use in a student satellite. The code works except the part where i am trying to reset the circuit.
In the sync process i have a signal, clear_input_ok, if this is set to '1' by the reset, the input_ok is supposed to be set to "1111" in the combinatorial process. This doesn't work though, I've asked my TA, and my professor, and they haven't fount a solution, and say that it should work. I will include source code. Thanks in advance!

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Voter is
    port(
        CLK : in STD_LOGIC;
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        c : in STD_LOGIC;
        d : in STD_LOGIC;
        reset : in STD_LOGIC;
        y : out STD_LOGIC;   
        status : out STD_LOGIC_VECTOR(2 downto 0)     
       
        );
end Voter;

--}} End of automatically maintained section

architecture Voter of Voter is
   
    SIGNAL input_ok: STD_LOGIC_VECTOR(3 downto 0);   
    SIGNAL clear_input_ok: STD_LOGIC;
    SIGNAL async_status: STD_LOGIC_VECTOR(2 downto 0);
    SIGNAL result_y: STD_LOGIC;
   
begin
   
    sync:   
        process (CLK,reset)
    begin
        if reset = '1' then   
            clear_input_ok <= '1';
        else clear_input_ok <= '0';
        end if;
        if clk = '1' then   
            status <= "000";
            y <= result_y;
            status <= async_status;       
        end if;
    end process sync;
   
    comb:
        process  (a,b,c,d, clear_input_ok)   
        VARIABLE vote_one : INTEGER RANGE    0 TO 4;   
        VARIABLE vote_null : INTEGER RANGE    0 TO 4;   
        VARIABLE failed : INTEGER RANGE 0 TO 4;
        VARIABLE result : STD_LOGIC;
    begin
        failed := 0;
        vote_one := 0;
        vote_null := 0;       
        async_status <= "000";
       
        if (clear_input_ok = '1') THEN   
            report("if statement runs!");
            input_ok <= "1111";
            end if;
        ------- inkrements voting variables----------   
        if (input_ok(0) = '1') THEN
            if (a='1') THEN
                vote_one:= vote_one +1;
            else vote_null:= vote_null +1;   
            end if;   
        else 
            vote_one := vote_one +1;
            vote_null := vote_null +1;
        end if;   
       
        if (input_ok(1) = '1') THEN
            if (b='1') THEN
                vote_one:= vote_one +1;
            else vote_null:= vote_null +1;   
            end if;   
        else 
            vote_one := vote_one +1;
            vote_null := vote_null +1;   
        end if;   
       
        if (input_ok(2) = '1') THEN
            if (c='1') THEN
                vote_one:= vote_one +1;
            else vote_null:= vote_null +1;   
            end if;   
        else 
            vote_one := vote_one +1;
            vote_null := vote_null +1;   
        end if;   
       
        if (input_ok(3) = '1') THEN
            if (d='1') THEN
                vote_one:= vote_one +1;
            else vote_null:= vote_null +1;   
            end if;   
        else 
            vote_one := vote_one +1;
            vote_null := vote_null +1;   
        end if;       
       
       
        ----- figure out result ------   
        if (vote_one = 4) THEN
            result := '1';
        end if;   
        if (vote_null = 4) THEN
            result := '0';
        end if;     
       
        -----check if there is contradicting values, and how many? and uppdate failed----------
        if (a /= result) OR input_ok(0) = '0' THEN
            input_ok(0) <= '0';
            failed := failed +1;
        end if;
        if (b /= result) OR input_ok(1) = '0' THEN
            input_ok(1) <= '0';
            failed := failed +1;
        end if;
        if (c /= result) OR input_ok(2) = '0' THEN
            input_ok(2) <= '0';
            failed := failed +1;
        end if;
        if (d /= result) OR input_ok(3) = '0' THEN
            input_ok(3) <= '0';
            failed := failed +1;
        end if;
       
        ----- uppdate status------
        if failed = 0 THEN
            async_status <= "000";
        end if;   
        if failed = 1 THEN
            async_status <= "001";   
        end if;
        if failed = 2 THEN
            async_status <= "010";
        end if;
        if failed > 2 THEN   
            async_status <= "111";
        end if;   
       
        ------uppdate result-------
        result_y <= result;   
    end process comb;
end Voter;
↧

Division on the last outputs in vhdl

February 20, 2014, 3:46 am
$
0
0
hi all,
counter count the number of input samples then the counter output (n) and i want to check if the numbers of samples is even do that (n*n) or if odd make that ((n*n)-1) will be something like that
Code:
signal dis : integer range 0 to 255 := 0;
 signal n  : integer range 0 to 255 :=0; 
if n mod 2=1 then   
  n_of samples<= ((n*n)-1); 
 else      n_of_samples <= n*n; 
 end if;   
 norm_dis <= dis / n_of_samples ;
(dis) signal will have values as (1,6,9,8,.....100) and the second signal (n) will have values as (0,2,8,9.......,200) and i want to fetch the two last outputs from the two signal (100,200) and divide 100/200.how can i write it in vhdl and how can overcome the divide by zero error.
i want help plz.
↧
↧

altera epf6016 5 Volt connection schematic

February 20, 2014, 6:32 am
$
0
0
Hi to all,
i were looking for a 5volt fpga device and i've found that ALTERA FLEX 6000 could be the right choice.
In order to configure and program this device it's necessary to connect the fpga to configuration device (eeprom, serial flash and so on) and download the configuration file via appropriate probe.

Is there any schematic of this kind of connection?
What kind of configuration device i have to use? EPC1441 is the right one?
Could you help me in resolving these issues?
Thanks a lot.
↧

Getting VGA to work on Arrow SoCKit

February 20, 2014, 7:11 am
$
0
0
Hello,


So I've been trying for a few weeks to make the output of the VGA to work correctly on my Arrow SoCKit but I've been encountering a few headaches. First of all, I am deriving the hardware system from the GHRD designed for Arrow SoCKit (http://www.rocketboards.org/foswiki/...eleaseContents). I only added the frame reader and clocked video output similarly to how it was done in the Linaro desktop example (http://www.rocketboards.org/foswiki/...roLinuxDesktop). I've attached my qsys file to this post.


I am currently using the linux kernel 3.9-rel the git repo at rocketboards.org. I have applied a patch that adds the altfb.c driver that interfaces with the video output reader synthesized on the FPGA (https://github.com/altcrauer/linux/c...5bdc83db216714). I have my own root file system based on Arch Linux (is this important?).


I have hooked up the VGA connector to the screen but I am not getting any image output. The way I try to activate it is by compiling the altfb.c into a kernel module and loading it during runtime by using "insmod" after activating the fpga bridges. I have poked the registers of the frame reader and see that is correctly activated and running however no screen output is created.


My question is this:


Am I missing anything in terms of linux drivers to be able to output an image on the screen? Am I missing something in terms of the hardware configuration (possibly the PLL frequency for the VGA is wrong)?


While I'm on the subject of IP blocks, where is it that I can get the linux drivers for all of these Altera IP blocks?


Thanks,

Alex
Attached Files
↧

How to evaluate Altera's openCL support?

February 20, 2014, 7:38 am
$
0
0
HI,

I've just downloaded Quartus-13.1+ + AOC to see what we can expect for our algorithms.
Using the free 30 days evaluation license works for Quartus, however AOC complains about a missing license file.

Is it possible to get a time-limited evaluation license for AOC, too?

- Reggi
↧
Viewing all 19390 articles
Browse latest View live
Search