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uClinux nios2 mmu

February 20, 2014, 11:37 am
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Hi.

I'm developing a system nios2 with mmu support and I can't make uClinux work.

This is the system nios ii build in Sopc Builder.

system_nios_ii.jpg

I can download the zImage.initramfs.gz

$ nios2-download -g zImage.initramfs.gz
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 1634KB in 23.8s (68.6KB/s)
Verified OK
Starting processor at address 0xC0400000

Then, I run nios2-terminal and...

$ nios2-terminal.exenios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)


Initializing cgroup subsys cpu
Linux version 3.7.0+ (usuario@cent24.16 BogoMIPS (lpj=120832)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource timer
NET: Registered protocol family 2
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered (default)
crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64
crc32: self tests passed, processed 225944 bytes in 3308320 nsec
crc32c: CRC_LE_BITS = 64
crc32c: self tests passed, processed 225944 bytes in -4244500 nsec
ttyAL0 at MMIO 0x803440 (irq = 1) is a Altera UART
console [ttyAL0] enabled, bootconsole disabled

in putty...

console [ttyAL0] enabled, bootconsole disabledttyJ0 at MMIO 0x803468 (irq = 2) is a Altera JTAG UART
spi_altera 803400.spi: master is unqueued, this is deprecated
spi_altera 803400.spi: base e0803400, irq 3
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mousedev: PS/2 mouse device common for all mice
mmc_spi spi32766.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
Warning: unable to open an initial console.
VFS: Cannot open root device "(null)" or unknown-block(0,0): error -2
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

and then nothing happens...

If anyone can help, I will be very grateful.

Attached the kernel configuration files and applications.

Thanks
Nicolás
Córdoba Argentina
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Trouble booting linux on SocKit development board

February 20, 2014, 12:00 pm
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We just got the SoCKit development board and I'm trying to get the factory provided Linux image to boot. I've written the image to a micro-SD card, set the BOOTSel and FPGA configuration mode switches as directed.When I power on the board I can see Uboot but it can find the kernel. I get the following messages: "** Unable to use mmc 0:1 for fatload **" and then "Wrong Image Format for bootm command" and "ERROR: can't get kernel image!". Any idea's what's going on.
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Send Data to DE2 memory

February 20, 2014, 12:02 pm
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I'm new in Verilog language.

I need to send data from Matlab to DE2 board via USB cable and store it in a memory.

Can someone help me with a book or text to I study it, or a simple code to do that?

Thanks
Danilo
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programming Cyclone III

February 20, 2014, 1:15 pm
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I was wondering if a simulation model excised for the Cyclone III device being programmed via passive serial. I am using the Cyclone III and using the MAX II device to auto program the FPGA from flash. I am trying to simulate my MAX II design, I found a model for the flash, but I need a model for the configuration pins on the FPGA.

If you know where one exists, I would greatly appreciate it.

Thanks.
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Turn off virual pin in DSPBA

February 20, 2014, 1:30 pm
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Hi all,

GPIO blocks in a DSPBA Simulink model generate in the modelname_dut.tcl file

source ./rtl/fixed/dut/fixed_dut.add.tcl
set_instance_assignment -name VIRTUAL_PIN ON -to In1
set_instance_assignment -name VIRTUAL_PIN ON -to Out1
set_instance_assignment -name VIRTUAL_PIN ON -to Out2
source "./rtl/fixed/dut/fixed_dut_fpc.add.tcl"

How can I turn VIRTUAL_PIN OFF. I want to do my own assignments in a different TCL script something like the following

source ./rtl/fixed/dut/fixed_dut.add.tcl
mytclpinassignment.tcl
source "./rtl/fixed/dut/fixed_dut_fpc.add.tcl"

-AA
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Nios II SBT for Eclipse not working under CentOS 6.5

February 20, 2014, 3:26 pm
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Recently I had to start working on a workstation with CentOS 6.5 as operating system. I installed the Quartus Software, version 11.1, but the Eclipse tools for Nios II just do not open. Then I installed Quartus 13.1, but problem still persists.

Here is the output I get when executing the eclipse-nios2 -Debug command from terminal:

Code:
Start VM: /opt/altera/11.1/quartus//linux/jre/bin/java
-Dosgi.requiredJavaVersion=1.5
-XX:MaxPermSize=256m
-Xms40m
-Xmx384m
-jar /opt/altera/11.1/nios2eds/bin/eclipse_nios2//plugins/org.eclipse.equinox.launcher_1.1.0.v20100507.jar
-os linux
-ws gtk
-arch x86
-showsplash
-launcher /opt/altera/11.1/nios2eds/bin/eclipse_nios2/eclipse
-name Eclipse
--launcher.library /opt/altera/11.1/nios2eds/bin/eclipse_nios2//plugins/org.eclipse.equinox.launcher.gtk.linux.x86_1.1.1.R36x_v20100810/eclipse_1309.so
-startup /opt/altera/11.1/nios2eds/bin/eclipse_nios2//plugins/org.eclipse.equinox.launcher_1.1.0.v20100507.jar
-exitdata 4d0054
-product org.eclipse.epp.package.cpp.product
-Debug
-perspective com.altera.sbtgui.ui.cPerspective
-vm /opt/altera/11.1/quartus//linux/jre/bin/java
-vmargs
-Dosgi.requiredJavaVersion=1.5
-XX:MaxPermSize=256m
-Xms40m
-Xmx384m
-jar /opt/altera/11.1/nios2eds/bin/eclipse_nios2//plugins/org.eclipse.equinox.launcher_1.1.0.v20100507.jar
Install location:
    file:/opt/altera/11.1/nios2eds/bin/eclipse_nios2/
Configuration file:
    file:/opt/altera/11.1/nios2eds/bin/eclipse_nios2/configuration/config.ini loaded
Configuration location:
    file:/opt/altera/11.1/nios2eds/bin/eclipse_nios2/configuration/
Framework located:
    file:/opt/altera/11.1/nios2eds/bin/eclipse_nios2/plugins/org.eclipse.osgi_3.6.1.R36x_v20100806.jar
Framework classpath:
    file:/opt/altera/11.1/nios2eds/bin/eclipse_nios2/plugins/org.eclipse.osgi_3.6.1.R36x_v20100806.jar
Splash location:
    /opt/altera/11.1/nios2eds/bin/eclipse_nios2/plugins/org.eclipse.platform_3.6.1.v201009090800/splash.bmp
Debug options:
    file:/home/cramos/.options not found
Time to load bundles: 5
Starting application: 1059
After the last line, the application never ever starts.

On the other hand, when executing the nios2-ide command, here is what I get:

Code:
/opt/altera/11.1/nios2eds/bin/nios2-ide: line 17: /opt/altera/11.1/nios2eds/bin/eclipse/nios2-ide: No such file or directory
/opt/altera/11.1/nios2eds/bin/nios2-ide: line 17: exec: /opt/altera/11.1/nios2eds/bin/eclipse/nios2-ide: cannot execute: No such file or directory
However, that directory does not exists (I attach an image of the contents of the Nios II directory).

Screenshot.jpg

I cannot seem to get the Nios II tools running on Linux, and there is no other error message to track down. If further information about the work environment is needed, I will gladly post it here.

Any help would be greatly appreciated. Thanks in advance.
Attached Images
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Is it feasible to use the GPIO of Cyclone IV to generate a 148.5MHz clock signal?

February 20, 2014, 5:19 pm
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Hi,
I am new to Altera FPGA Forum.
I managed to design a video signal source by using the Altera FPGA for generating test signals. It would send a 1080p60 digital video signal in BT.1120 20bit data format. Meanwhile, I managed to generate a 148.5MHz clock from altera PLL and use the GPIO as an output for this 148.5MHz clock. A Cyclone IV FPGA would be used in our project.

My Questions:
I. Is it feasible for the GPIO to generate a 148.5MHz clock signal?
II. Which parameter in Altera Cyclone Handbook would tell me the Max IO speed of a GPIO?

I am sincerely looking forward to your reply.

Naroah
Feb/21/2014
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Debugging TDO on Cyclone V

February 20, 2014, 5:30 pm
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Hello,

I am making my first attempt at a custom Cyclone V 5CEBA4U15 board after using a rival FPGA vendor for several years, so I have probably made some rookie mistakes. The JTAG chain is broken, and I'm having a hard time understanding why. I have set MSEL to 00000.

I have scoped the TCK, TMS, and TDI lines going to the chip, and can see each of them twiddling as expected when I click the "Test JTAG Chain" button in the Quartus JTAG Debugger or use the "jtagconfig" program at the command line. Signal integrity looks decent on the scope. Unfortunately, TDO never moves, so the tools correctly report that the JTAG chain is broken.

Since it's a BGA, I don't have complete visibility of these signals all the way to/from the chip package, but my fab house did x-ray them today, and they looked fine. I am probing the signals in the last via before they enter the BGA. I have tried cutting the TDO trace to make sure nothing else is holding it down, and it is not shorted to power/ground.

VCCPD3A, VCCPGM, and VCCIO3A are measuring 3.3v. VCC_AUX is measuring 2.5v, and VCC is measuring 1.1v . The I/O pads that I can probe are showing weak pull-up to their respective VCCIO, as expected. The configuration signals are as follow:

MSEL = 00000
nCONFIG = high
nSTATUS = low (there is a pull-up resistor on it, so the FPGA is actively pulling it low)
nCE = grounded
CONF_DONE = low
DCLK = low

Since I am just using JTAG configuration, I had assumed that the power supply ramp time was irrelevant, but it is measuring approximately 60ms for the 3.3v rail and ~20ms for the 1.1v rail.

What debugging steps are recommended from a situation like this, when TDO is unresponsive? I'm not quite sure what to try next.

Thanks for your time,
Morgan
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image processing

February 20, 2014, 10:19 pm
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we r doing image processing for that we r going to use cyclone III EP3C120F780C7 KIT with daughter card hsmc dvi

1] It is possible for us to use store image from the computer?
2]If it is then can we access those images through jtag to the fpga for processing
3]please tell us whether this could be done like in matlab how we give path and access images similar thing would be possible using nios ii

4]we want to store same process image on to the pc


Please tell above things would be possible
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get work a LCD 16207 on cyclone IV Gx

February 20, 2014, 11:20 pm
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Hello,

I would like to send a character or a chain character to a LCD 16207 16x2. I have integrated the Lcd, the nios on QSYS and everything, I have created a project on Quartus II and assigned all pins correctly.
In Eclipse, I wrote a program just for cleaning the LCD but It doesn't work..
All functions and drivers are already written in file.h, I just have to initialize some variables but even tought, It doesn't work. Does anyone already has a problem like that and can help me?

Thanks a lot!
Tiff.
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shell script does not work with newer version

February 21, 2014, 2:47 am
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Hi!

I worked with the QuartusII WebEdition 8.1. I used a shell-script to synthesize my code using the SOPC builder. Everything worked fine.

Now I changed to the 12.1sp1 Webedition-version (because it has the sopc-builder) and the same script doesn´t work anymore.

I changed of course the enviroment variables to the new pathes of the 12.1sp1 version. But it doesn´t recognize the path.

I invoke my shellscript via a batchfile that contains:

Code:
@ %QUARTUS_ROOTDIR%\bin\cygwin\bin\bash.exe --rcfile ../Scripts/SOPC.sh
And then the shellscript contains:

Code:
. $QUARTUS_ROOTDIR/sopc_builder/bin/nios_bash
With the 8.1 version it works perfectly but with the 12.1sp1 occurs the error "no such file o directory" (referring to the "nios_bash") although the file exists and is at the right directory.
What did change between this versions, that it doesn´t work?

Thanks for any suggestions

(I´m using windows 7 64 bit.)
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Cyclone IV external memory design guideline/tutorial

February 21, 2014, 6:01 am
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Hi,

i have the cyclone IV EP4CE10 starterkid.

I would like to add now the onboard SDRAM chip to my design. I found lots of information for other devices, but i got more confused.
Does anyone know where i can get a reference book or a tutorial design guideline, primary for this device type ?

Cheers,
Tim
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Cyclone IV GX Dev Kit - Errata / Faults / Problems

February 21, 2014, 9:09 am
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Cyclone IV GX Dev Kit - Errata / Faults / Problems
DK-DEV-4CGX150N

I'm just going to post stuff here as I find it so that other people have a chance of finding it when they hit similar problems.

I'm afraid I've given up creating problem reports with Altera as they just get ignored which is no help to other people when they hit the same issue. Altera, if you actually read this, please put an Errata document with this info on the dev kit page. It makes you look worse not having it than it does publishing this information.
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DDR3 Migration between device families

February 21, 2014, 3:02 pm
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Hi everyone,

I ran into an issue and searched the forum but unfortunately didn't find the answer. I was able to figure it out so I thought I'd post the solution in case someone else came across this. I should note that I am running Quartus 13.1.2 build 173.

The issue is that I'm migrating a design from Stratix IV to Stratix V. The DDR3 Controller with Uniphy was created in a project targeting a Stratix IV. When migrating to Stratix V, the controller remains set for Stratix IV. The problem is that the Quartus error was not immediately obvious. Here is the error it gave:

Error (12024): WYSIWYG primitive "obuf_ba_0" is not compatible with the current device family
Error (12024): WYSIWYG primitive "obufa_0" is not compatible with the current device family
Error (12024): WYSIWYG primitive "pseudo_diffa_0" is not compatible with the current device family

By default, the Device Family is hidden in the Megawizard. Even when it isn't, changing the family does not set all of the correct settings for the new family. I'm guessing this is because it would have to make assumptions about what settings to choose that may change the behavior too much. Perhaps it's the number of software checks it would have to run.

The solution is to generate the IP from scratch inside a Quartus project targeting the correct device family. Might be an obvious solution but it didn't follow directly from the error messages so here we are.

Enjoy!
Scott
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USB clones and JTAG Indirect SFL mode

February 21, 2014, 2:46 pm
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Hi,

Trying to figured out things about my issue about Programming EPCS JTAG Indirect using SFL ( http://www.alteraforum.com/forum/showthread.php?t=44011 ), I did many searches in Altera forum, but elsewhere too.

Seeing this thread http://www.alteraforum.com/forum/sho...t=41023&page=2, I came to the conclusion that maybe my problem is related to my USB Blaster itself, I'm using an $9 clone (with sandpapered cpu with 244 buffer) ...
Continue searching, I found this thread discussing about tons of different clone flavors : http://www.eevblog.com/forum/microco...programmer/15/

So, I decided to order a new clone which, this time, use an FT235+CPLD, I choose this one :

http://www.ebay.com/itm/FT245-CPLD-U...item2a2323c811

(hoping I've made good decision compared to more expensive ones)

There were also Cypress FX2 clones, but I feared that even if hardware will work, maybe the firmware for those are not included since they are mostly generic EZ-USB Dev boards.

Can someone confirmed me the following things :

1) Cheap clone (with sandpapered cpu with 244 buffer) will never be compatible with JTAG SFL mode ? (If my conclusion is good)
2) Is all or most of the FT245 works fine in JTAG SFL mode ?

Thanks in advance,
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Where is the "dedicated clock output pin" of Cyclone II FPGA?

February 21, 2014, 10:24 pm
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Hi,
I am now using a customed Cyclone II Evaluation Module. The FPGA is EP2C8Q208C8.
I managed to use the ALTPLL module to generate a 150MHz clock signal. Meanwhile, the clock signal would be output to a DAC IC. By assigning the 150M-clock-output into a GPIO, I received a warning from Quartus II : "...Use PLL dedicated clock outputs to ensure jitter performance". I do know there were dedicated clock output for each PLL. However, I don't know which pin it is. Although I tried to search the "dedicated clock output pin" in Cyclone II Handbook, the result seems meaningless for me.
Could you please tell me which pin in EP2C8Q208C8 is the "dedicated clock output" for PLL1?

Naroah
Feb/22/2014
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About TimeQuest Unconstrained Paths

February 22, 2014, 12:31 am
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1.jpg2.jpg
I want to synchronize the clock"in"to the clock"clk",and get the clock trigger the data.
But after compiled ,the Report give the hint as shown in figure . "inst" is not a base clock, how to deal with it?
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SUm of table

February 22, 2014, 3:56 am
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Hi,

Please can you help me to write a Verilog code to calculate sum of table, I have a code that’s calculate with this manner.
generate
if(z == 1)
assign x = y[0];
else if (z == 2)
assign x = y[0] + y[1];
else if (z == 3)
assign x = y[0] +y[1] + y[2] ;
endgenerate
I need to let’s this code a generic using a boucle for to calculate sum of table using always block.

Thank you for your helps.
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multiple constant drivers for net erro

February 22, 2014, 7:04 am
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Hi,
I have this code
HTML Code:
reg signed [DATA_WIDTH+COEF_WIDTH+1:0] final_additions [(NUM_OF_TAPS/4)-1:0];  // two multiply results added together and registered
reg signed [DATA_WIDTH+COEF_WIDTH+1:0] final_result;  // sum of final_additions
wire signed [DATA_WIDTH+COEF_WIDTH+1:0] final_result_temp;
wire signed [COEF_WIDTH-1:0] coefficients [0: (NUM_OF_TAPS) -1];   
 
genvar Counter_Result;
                generate
                for(Counter_Result = 0; Counter_Result < ((NUM_OF_TAPS/4)-1); Counter_Result=Counter_Result+1)
                begin : the_final_reult
                                always @ (posedge clk or posedge reset)
                                begin
                                                if (reset)
                                                begin
                                                                final_result_temp<= 0;
                                                end
                                                else if (clear == 1)
                                                begin
                                                                final_result_temp <= 0;
                                                end
                                                if (Counter_Result == 0)
                                                begin
                                                                final_result_temp <= final_additions[Counter_Result];
                                                end
                                                else
                                                begin
                                                                final_result_temp <= final_result_temp+final_additions[Counter_Result];
                                                end
                                end
                end
                endgenerate
                always @ (posedge clk or posedge reset)
                begin
                                if (reset)
                                begin
                                                final_result <= 0;
                                end
                                else if (clear == 1)
                                begin
                                                final_result <= 0;
                                end
                                else
                                begin
                                                final_result <= final_result_temp;
                                end
                end
When i launch the compilation i get this error:
Error (10028): Can't resolve multiple constant drivers for net "final_result[33]" at custom_FIR.v(255).
How can i correct this erros.

Thank you
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Quartus II "No devices installed"

February 22, 2014, 1:18 pm
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I downloaded Quartus II 13.0 to use with the Cyclone II. I downloaded the device family for the Cyclone II. It is a QDZ file? Where do I put this file so I can compile a program?
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