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DE2-115 lab exercises solutions

May 2, 2014, 9:27 am
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Dear all,

I ordered a DE2-115 board. In the CD with board, there are ten lab sections which will be very beneficial for me to learn this FPGA based system.

The lab sections only contains task, but there is no design solution files.

Could anyone know where I could get the design solution files only for my reference?

Thanks!
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DE2-115 lab exercises solutions

May 2, 2014, 9:29 am
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Dear all,

I ordered a DE2-115 board. In the CD with board, there are ten lab sections which will be very beneficial for me to learn this FPGA based system.

The lab sections only contains task, but there is no design solution files.

Could anyone know where I could get the design solution files only for my reference?
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DE2-115 lab exercises solutions

May 2, 2014, 9:31 am
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Dear all,

I ordered a DE2-115 board. In the CD with board, there are ten lab sections which will be very beneficial for me to learn this FPGA based system.

The lab sections only contains task, but there is no design solution files.

Could anyone know where I could get the design solution files only for my reference?

Thanks!

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DE2-115 Will Not Output Audio

May 2, 2014, 12:01 pm
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I am trying to output audio from the DE2-115 board. I have the audio and the external clock in my .qsys file, and I have been using the example C code given by the Audio core documentation. I want to create a specific tone held in an array named c, and output it to the board. I am able to open the audio device, but the code does not seem to be able to write the data to the left and right buffers. Is there a way to do this?

Here is my code:

alt_up_audio_dev * audio_dev;
/* used for audio record/playback */
unsigned int l_buf;
unsigned int r_buf;
// open the Audio port
audio_dev = alt_up_audio_open_dev ("/dev/audio_0");


if ( audio_dev == NULL)
alt_printf ("Error: could not open audio device \n");
else
alt_printf ("Opened audio device \n");
/* read and echo audio data */
alt_up_audio_reset_audio_core(audio_dev);
int count = 0;
while(1)
{


// write audio buffer
int sound_size = 50;
int r_size = alt_up_audio_write_fifo_space(audio_dev, ALT_UP_AUDIO_RIGHT);
int l_size = alt_up_audio_write_fifo_space(audio_dev, ALT_UP_AUDIO_LEFT);
if((r_size > sound_size) && (l_size > sound_size)){
alt_up_audio_write_fifo_head(audio_dev, c, ALT_UP_AUDIO_RIGHT);//write the contents of the tone array to right buffer
alt_up_audio_write_fifo_head(audio_dev, c, ALT_UP_AUDIO_LEFT);


}


}
}

Sidebar: Should the audio be memory-mapped or streaming if I already have the arrays written somewhere and I just want to output them?
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The question about bidirectional port

May 2, 2014, 2:05 pm
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In my design, I have a inout port. Then I search it, found most examples, they only put the high impedance for output direction as (case 1):

inout [7:0 ]data_io;

reg [7:0] out_a;
wire [7:0] in_b;
reg rnw;

assign data_io = (rnw==1'b0) out_a : 8'bZ; /// when read, assign io as high impedance
assign in_b = data_io;


But I think we may also put high impedance in both direction like (case 2):

inout [7:0 ]data_io;

reg [7:0] out_a;
wire [7:0] in_b;
reg rnw;

assign data_io = (rnw==1'b0) out_a : 8'bZ; /// when read, assign io as high impedance
assign in_b = (rnw==1'b1) data_io : 8'bZ; /// when write, read high impedance



So my question is, will put high impedance in both directions (like case 2) cause problems?
My understanding is it won't cause problem. The difference between case 1 and case 2 is, in case 1, the "in_b" will equal the output date during write operation.

Thanks.
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PCI express gen3 x8 Avalon-MM 256 bit DMA core multiple request hang issue

May 2, 2014, 6:25 pm
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In attempting to perform multiple DMA requests in parallel with the example design, it seems that something in the core ends up in an inconsistent state. After performing a single DMA read of 128 bytes, the EPLAST value is written correctly to the beginning of the descriptor table stored in root port memory. The DMA operation can be repeated afterwards just by setting the start bit in the control register. However, if I request a read of 128 bytes and a read of 1024 bytes in parallel with two descriptors in the table, this EPLAST write never takes place and the core seems to be in an inconsistent state - setting the start bit is ignored and no further DMA requests can be initiated without reconfiguring the FPGA. Does anyone know if this issue lies in the DMA core itself or in the descriptor controller?

If it's in the descriptor controller, it's not really a big problem because I'm eventually going to write my own. However, I do need the DMA core working, and I have already found one bug in it so far.
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Modifying DE2 TV demonstration program

May 3, 2014, 1:40 am
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Hello,

I am using V2.0 of the DE2_TV demonstration program provided with the cyclone II CD package as a basis for video processing for a project.
Within the program it downsizes the input video feed from 720x480 to 640x480. (squashes image horizontally I believe)
The resultant 640x480 signal is put to the VGA port for output.

I would like to know if it is possible to maintain the original 720x480 resolution (no downsizing) through to the output.
I've tried messing around with some values, setting the divisor quotient and remainder (which determine pixel skips or swaps in order to achieve resizing) to constant 0 and changing the allocated memory space from 640 to 720 (initially WR1_MAX_ADDR(640*507))

Does anyone know firstly if it's possible (does VGA output support this resolution...?) and what I would need to do it?
Would it be possible to output in QVGA (800x600) and create black borders around the 720x480 image?

Cheers

Finn
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modifying Web server for DE2 115 kit using quartus II

May 3, 2014, 5:53 am
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Hi,,
We are working on a project using the available "web server" demo program in DE2-115 kit manual. we have created our own webpage and tried to fuse in the same way as the one available with demo program. It is getting built properly and able to assign IP address for the kit. but we are getting problem saying 404 "not found" error when we want to access the website in other syatems connected to the same network. Please someone help us in resolving this error.

Thanking in advance....

VEER......:confused::confused::confused::confused:
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Frame Buffer Parameter

May 3, 2014, 9:08 am
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framebuf.JPG I am using Frame Buffer Megacore. I want to store a 640*480 pixels frame to sdram. As in the picture, I set Maximum packet length = 10 symbols. While 1 symbol = 3 color planes (= 1 pixel) => we have 640*480/10 packets per frame. That is so conflicted with Number of packet buffered per frame =1 which I set as in the picture. Can anyone explain it for me?
Attached Images
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Writing SDRAM from custom IP using Avalon MM write Template

May 3, 2014, 4:20 pm
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Hello,

I want to write SDRAM through my custom hardware IP. I am using the Master Templates for this. I am writing using custom hardware and reading using NIOS, but my bios doesn't read the correct value.
Below is my code for writing into SDRAM.
I want to write on the click of a button (coe_switch[3]). I have one more doubt, "myBuffer_control_write_write_base" should be the base address for SDRAM or offset or base+offest.

reg searchForSync;
always @(posedge csi_clk or negedge rsi_rst) begin
if(!rsi_rst) begin
click <= 0;
searchForSync <= 0;

end else begin
if(coe_switch[3] == 0) begin
searchForSync <= 1;
myBuffer_control_write_fixed_location <= 0;
myBuffer_control_write_write_base <= 32'h00000000;
myBuffer_control_write_write_length <= 8;
myBuffer_control_write_go <= 1;
myBuffer_user_write_buffer_input_data <= 1;
myBuffer_user_write_write_buffer <= 1;
end
if(searchForSync == 1) begin
myBuffer_user_write_buffer_input_data <= 1;
myBuffer_user_write_write_buffer <= 1;
myBuffer_control_write_go <= 0;
if(asi_stin_sop_reg[319] == 1) begin

end
end
end
end

Please let me know if I am doing something wrong.
Please suggest.
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Modelsim Altera Starter Edition problem

May 4, 2014, 2:05 am
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Hello,

I'm a newbie about QuartusII and Modelsim.
This is my problem: in my VHDL entity there are eight signals (1bit wide): IN0,IN1,IN2,IN3...IN8
I would like to force their values like a bytes (in decimal or hex values) but when I use Modelsim I can only set their values one bit at a time.
I tried to combine them in a but it isn't possible to force a combined signal (Modelsim doesn't do anything when i press FORCE on the combined signal alias).
Is it possible to force the eigth values like a single byte?
Best regards.
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Rgb444

May 4, 2014, 9:51 am
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rgb.JPGI dont know how the RGB444 is transfered in this situation. The parameter Bits per pixel per color plane = 8 -> RGB888 isn't it? So, it is conflicted with RGB444 output format?
Attached Images
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Device out of range. Compilation error after changing device assignment

May 4, 2014, 1:16 pm
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Compilation error after changing the device assignment (and allowing the removal of all location assignments) from a Cyclone III EP3C10E144C8 to a Cyclone II EP2C35F672C6. This is a monstrously long one-line error message (I added red color for emphasis):

Code:
Error (12252): SPI_bridge_2: "Device" (device)  (EP3C10E144C8) out of range. Valid ranges: [Unknown:Unknown,  EP2C15AF256A7:EP2C15AF256A7, EP2C15AF256C6:EP2C15AF256C6,  EP2C15AF256C7:EP2C15AF256C7, EP2C15AF256C8:EP2C15AF256C8,  EP2C15AF256I8:EP2C15AF256I8, EP2C15AF484A7:EP2C15AF484A7,  EP2C15AF484C6:EP2C15AF484C6, EP2C15AF484C7:EP2C15AF484C7,  EP2C15AF484C8:EP2C15AF484C8, EP2C15AF484I8:EP2C15AF484I8,  EP2C20AF256A7:EP2C20AF256A7, EP2C20AF256I8:EP2C20AF256I8,  EP2C20AF484A7:EP2C20AF484A7, EP2C20AF484I8:EP2C20AF484I8,  EP2C20F256C6:EP2C20F256C6, EP2C20F256C7:EP2C20F256C7, EP2C20F256C8:EP2C20F256C8,  EP2C20F256I8:EP2C20F256I8, EP2C20F484C6:EP2C20F484C6, EP2C20F484C7:EP2C20F484C7,  EP2C20F484C8:EP2C20F484C8, EP2C20F484I8:EP2C20F484I8, EP2C20Q240C8:EP2C20Q240C8,  EP2C35F484C6:EP2C35F484C6, EP2C35F484C7:EP2C35F484C7, EP2C35F484C8:EP2C35F484C8,  EP2C35F484I8:EP2C35F484I8, EP2C35F672C6:EP2C35F672C6, EP2C35F672C7:EP2C35F672C7, EP2C35F672C8:EP2C35F672C8,  EP2C35F672I8:EP2C35F672I8, EP2C35U484C6:EP2C35U484C6, EP2C35U484C7:EP2C35U484C7,  EP2C35U484C8:EP2C35U484C8, EP2C35U484I8:EP2C35U484I8, EP2C50F484C6:EP2C50F484C6,  EP2C50F484C7:EP2C50F484C7, EP2C50F484C8:EP2C50F484C8, EP2C50F484I8:EP2C50F484I8,  EP2C50F672C6:EP2C50F672C6, EP2C50F672C7:EP2C50F672C7, EP2C50F672C8:EP2C50F672C8,  EP2C50F672I8:EP2C50F672I8, EP2C50U484C6:EP2C50U484C6, EP2C50U484C7:EP2C50U484C7,  EP2C50U484C8:EP2C50U484C8, EP2C50U484I8:EP2C50U484I8, EP2C5AF256A7:EP2C5AF256A7,  EP2C5AF256I8:EP2C5AF256I8, EP2C5AT144A7:EP2C5AT144A7, EP2C5F256C6:EP2C5F256C6,  EP2C5F256C7:EP2C5F256C7, EP2C5F256C8:EP2C5F256C8, EP2C5F256I8:EP2C5F256I8,  EP2C5Q208C7:EP2C5Q208C7, EP2C5Q208C8:EP2C5Q208C8, EP2C5Q208I8:EP2C5Q208I8,  EP2C5T144C6:EP2C5T144C6, EP2C5T144C7:EP2C5T144C7, EP2C5T144C8:EP2C5T144C8,  EP2C5T144I8:EP2C5T144I8, EP2C70F672C6:EP2C70F672C6, EP2C70F672C7:EP2C70F672C7,  EP2C70F672C8:EP2C70F672C8, EP2C70F672I8:EP2C70F672I8, EP2C70F896C6:EP2C70F896C6,  EP2C70F896C7:EP2C70F896C7, EP2C70F896C8:EP2C70F896C8, EP2C70F896I8:EP2C70F896I8,  EP2C8AF256A7:EP2C8AF256A7, EP2C8AF256I8:EP2C8AF256I8, EP2C8F256C6:EP2C8F256C6,  EP2C8F256C7:EP2C8F256C7, EP2C8F256C8:EP2C8F256C8, EP2C8F256I8:EP2C8F256I8,  EP2C8Q208C7:EP2C8Q208C7, EP2C8Q208C8:EP2C8Q208C8, EP2C8Q208I8:EP2C8Q208I8,  EP2C8T144C6:EP2C8T144C6, EP2C8T144C7:EP2C8T144C7, EP2C8T144C8:EP2C8T144C8,  EP2C8T144I8:EP2C8T144I8]
The error doesn't make sense because it's calling out the old device. I notice that old value EP3C10E144C8 lingers in these two files:

SPI_bridge_2.qsys (which was not modified by compilation)
Code:
<parameter name="device" value="EP3C10E144C8" />
SPI_bridge_2.sopcinfo (which was modified by compilation)
Code:
<parameter name="AUTO_DEVICE">
  <type>java.lang.String</type>
  <value>EP3C10E144C8</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
 </parameter>
It's as if I can't change the device. Should I start a new project when porting from Cyclone III to Cyclone II?
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hi! Understanding a coding (counter), help

May 4, 2014, 2:08 pm
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entity counter is
generic (
n : natural := 4;
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(n-1 downto 0)
);
end entity;
architecture rtl of counter is
signal value : std_logic_vector(n-1 downto 0);
begin
PROCESS(clock, reset_n)
begin
if (reset_n = ’0’) then
value <= (OTHERS => ’0’);
elsif ((clock’event) and (clock = ’1’)) then
value <= value + 1;
end if;
end process;
Q <= value;
end rtl;
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How to force Qsys library component to use registers for SCFIFO

May 4, 2014, 4:56 pm
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Hello,

I am trying to implement a Qsys design but I am running out of M9K RAMS, the design uses 2 more M9K than those
available in the FPGA.

The design uses 2x sgdma. I looked at the RAM resource use and the sgdma has a command FIFO of 45 x 2 bits. This uses
2 x M9K and is implemented with a SCFIFO.

I would like to force these instances of SCFIFO to use registers instead of M9K since I have plenty of spare regs. I should
be able to set the parameter "use_eab" to "OFF". I am new to Qsys and can not find out how or where to set this parameter
for these particular instances of SCFIFO.

I believe it would be easy to set the parameter if the SCFIFO was instantiated as a Mega Function but that sort of defeats
the purpose of Qsys.

Any help would be much appreciated.

Thanks

Mike
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Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/utils

May 4, 2014, 9:29 pm
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Any ideas why it may happen?
I just added a PLL to my project based on golden design for Cyclone V SoC devkit. Now, I cannot move forward in compiling the design even when removing PLL instance from top level module.

--Dmitry

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/utils_profiling.c, Line: 538

Internal Error
Stack Trace:
0x119632: vpr_qi_jump_to_exit + 0x58 (fitter_vpr20kmain)

0x43daaf: vpr_final_exit + 0x8 (fitter_vpr20kmain)
0x4460e2: vpr_exit_at_line + 0x57 (fitter_vpr20kmain)
0x1d7c58: profile_close_bin + 0x338 (fitter_vpr20kmain)
0x235dc3: vpr_report + 0x13 (fitter_vpr20kmain)
0x792f8: VPR_QI_FACADE::vpr_qi_main() + 0x28 (fitter_vpr20kmain)
0x3d870: fitapi_run_vpr + 0x60 (fitter_fitapi)
0x3febe: FSV_EXPERT_BASE::place_and_route(bool*) const + 0x16e (fitter_fsv)
0x444e0: FSV_EXPERT_BASE::invoke_fitter() const + 0x17e0 (fitter_fsv)
0x3e402: fsv_execute + 0x292 (fitter_fsv)
0x2cac5: fmain_start(CMP_FACADE*) + 0x565 (fitter_fmain)
0x1b840: qfit_execute_fit(QCU_FRAMEWORK*, QFIT_FRAMEWORK*) + 0x150 (comp_qfit_legacy_flow)
0x15afd: QFIT_FRAMEWORK::execute() + 0x2ad (comp_qfit_legacy_flow)
0x25651: qfit_legacy_flow_run_legacy_fitter_flow + 0x1a1 (comp_qfit_legacy_flow)

0x2e8f6: TclInvokeStringCommand + 0x76 (tcl8.5)
0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5)
0x34310: TclEvalEx + 0x4f0 (tcl8.5)
0x34d13: TclEvalObjEx + 0x393 (tcl8.5)
0x3ac31: Tcl_EvalObjCmd + 0x91 (tcl8.5)
0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5)
0x73abf: TclExecuteByteCode + 0x151f (tcl8.5)
0xb5bc7: TclObjInterpProcCore + 0x107 (tcl8.5)
0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5)
0x73abf: TclExecuteByteCode + 0x151f (tcl8.5)
0xb5bc7: TclObjInterpProcCore + 0x107 (tcl8.5)
0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5)
0x34310: TclEvalEx + 0x4f0 (tcl8.5)

0x98c70: Tcl_FSEvalFileEx + 0x230 (tcl8.5)
0x98d6e: Tcl_EvalFile + 0x2e (tcl8.5)
0xff62: qexe_evaluate_tcl_script(char const*) + 0x43b (comp_qexe)
0x15515: qexe_do_tcl(QEXE_FRAMEWORK*, char const*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > > const&, bool, bool) + 0x507 (comp_qexe)
0x16352: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >*, bool) + 0x542 (comp_qexe)
0x32bbe: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >*, bool) + 0x7b1 (comp_qcu)
0x18b1f: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x641 (comp_qexe)
0x9517: qfit2_main(int, char const**) + 0xe7 (quartus_fit)
0x3bb9a: msg_main_thread(void*) + 0x10 (ccl_msg)
0x75bc: thr_final_wrapper + 0xc (ccl_thr)

0x3c801: msg_thread_wrapper(void* (*)(void*), void*) + 0x5b (ccl_msg)
0x18bf5: mem_thread_wrapper(void* (*)(void*), void*) + 0xc5 (quartus_fit)
0xf41d: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x799c: thr_thread_wrapper + 0x15 (ccl_thr)
0x4e41d: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0x96 (ccl_msg)
0x21ec5: __libc_start_main + 0xf5 (c.so.6)
0x8d69: __gxx_personality_v0 + 0x311 (quartus_fit)


End-trace


Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Altera DE4 PCIe example tutorial design doesn't detect by lspci command

May 4, 2014, 10:31 pm
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I'm a graduate student of University of Moratuwa, Sri Lanka. Recently we bought an Altera DE4 board from terrasic. I have connected the DE4 board to a PC having linux version 3.13.0 and built up the PCIe design example given by the altera using Quartus II 13.1. After programming the board with the generated "de4_pcie_tutorial.sof" file, I have rebooted the PC. But still the "lspci" command does not recognize the board.
Could you please advise me on this whether there is any special issue to be considered or not? Thank you very much for your help in advance.

thanks & regards,
Kavinga Upul
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About the "High-Speed I/O Specification" in Stratix5 datasheet

May 5, 2014, 9:58 am
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Table36 in the datasheet lists the high-speed I/O specifications for stratix5 devices, does this mean differential high-speed I/O only? what about single-ended I/O speed?

I want to implement a 32bit*312.5MHz single-ended interface, can anyone recommend an FPGA model for me? tks!
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May I use a reg variable to indicate the bus bit ?

May 5, 2014, 11:45 am
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I have a design, I want to use a reg variable to control another bus bit like：

reg [2:0] a;
reg [7:0] b;
reg c;
reg [2:0] d;

case 1:

c <= b[a];


case 2:

d <= b[a:a-2];


It seems case 1 is feasible but case 2 I confronted the errors, which complains that "a" is not a constant, why?

Thanks.
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DK-N2EVAL-3C25N board with Quartus II / Nios II

May 5, 2014, 12:52 pm
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Hi.
I got a DK-N2EVAL-3C25N board some days ago and have some problems to understand how all the software get used.
When i get it right, the board has not really a microcontroller on it, the Nios II 3C25 microprocessor runs in the fpga. Thats really confusing for me, because i had only boards before with an external microcontroller.
There is some documentation, but its not really good and most of the stuff is broken, yes broken. And there are many conflicts with the versions. Some stuff runs only with the version 11.1, some other stuff with 9.1 and so on.
There are examples for using the nios microcontroller and c/c++ but that was not really the plan why i bought a fpga board. The plan was to program vhdl/verilog. There are not really good examples how to create an project with Quartus II
and its even more confusing, that the microcontroller is in the fpga. Usually you have source for the external microcontroller and code for the fpga and each communicate with each other by defined output pins.
But how does that work with that combination?
There is not really any kind of usefull example or documentation only for using the Nios II 3C25 microprocessor. I could compile the c code and run it with the usb-blaster on my device.
But how does it work to use microprocessor with verilog in combination?
And how can i use the megacore libs? There is a lot of marketing bla, but that is not helpfull. Its nice when nice girls explain me how magic the megacore libs are, but i would prefer when they tell me how to use it.

And the worst thing are the examples.
I downloaded the Altera's Video and Image Processing Suite, because it has everything what i need. I can run the binaries but i cant compile the code(11.1 and 9.1). I tried nearly every version of Quartus II and in each version something else is missing. It looks like that parts of the example are missing. I looked in the board here and many people complaint about that in different examples. One guy asked for the missing stuff and the altera support send him the missing parts after he asked many times. Examples which don't work are useless.

I read now many documents about the board, the Quick Start Guide, the User Guide, the My First Nios II Software Tutorial, the My First FPGA Tutorial abd many more but.

Does anyone has some examples or documents how to use the microcontroller in combination with verilog.
Can someone explain me how to use the megacore libs and are there list of what is included?
And why are so many examples from altera uncompleted?
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