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Reed solomon IP

May 6, 2014, 2:50 am
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Hi,

I am using the Altera user guide for the Reed-Solomon Compiler
and I want to know for the Reed-Solomon decoder why the minimum value for the number of symbols per
codeword is 5 ? because i want that the decoder receives codeword with only 4 symbols.

thanks
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erreur VHDL

May 6, 2014, 6:55 am
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Hello!

In fact,i have a small problem but I don't understand what I should do

here is my code:
Code:
library ieee ;use ieee.std_logic_1164.all ;
use ieee.std_logic_signed .all ;


entity M is
port(
        clk        : in  std_logic ;
                rst        : in  std_logic ;
                data        : in  std_ulogic_vector(1 downto 0);
                CD            : in std_logic_vector(3 downto 0);
                s                : out std_logic_vector (1 downto 0));


end entity ;


architecture beh of M is


signal com :std_logic_vector(3 downto 0);


begin


code :process(clk,rst)


begin
   
    if (rst='1') then
      (others=>'0')<=data;
      --data<='0' !!! ;
      (others=>'0')<=CD;
      --"0000"<=CD ;
      s  <=(others=>'0');
    else
        for i in 0 to 3 loop
     
          if (clk'event and clk='1')then
 
              --for i in 0 to 3 loop
 
                  com(i)<= not(CD(i) xor data) ;
     
          end if ; 
        end loop ;
             
    end if ;
    end process ;
    s<=com(i) ;
    end architecture ;
This is my problem :

"""Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type"""


Thanks in advanced.
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Data Exchange between FPGA and NIOS2

May 6, 2014, 8:59 am
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Hi Everyone,
I want to implement data exchange between NIOS2 and FPGA . For exampe, transfer data form NIOS2 to FPGA with a Dual Port RAM. Is it possible to do that ?
and how to make that happen? I am waitting for idea, thank U!

NIOS2 (ram1)<--> FPGA(on chip ram2)
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Position Indepedent Code for Nios

May 6, 2014, 10:58 am
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Hello,

I was using Quartus 13.0sp1 and had no problem compiling a library project with the compiler option -fpic.
I just switched to Quartus 13.1 and now I receive the error:
error: position-independent code requires the Linux ABI

Why is this happening? Also, when I try to use -mno-gpopt it says that the option is not recognized.
In fact, none of my old projects work, with the error :
nios2-elf-g++: error: unrecognized command line option '-EL'

I don't even know what that option does, but why all of a sudden are flags that are automatically generated
in the makefile from 13.0 not working in 13.1?

Why is the compiler throwing errors all of a sudden? Do I have to switch back to an earlier version of Quartus?
Thanks,
Jonah
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Create control three elevators of a building of 15 floors.

May 6, 2014, 11:06 am
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I need to create a code in vhdl to control 3 elevators in a building of 15 floors.
At first everyone is in position 0 and only the elevator E1_POS should be called , the other lifts will stand .
The data from these ports are :


Clock , Reset : IN STD_LOGIC ;
C_orig : IN INTEGER RANGE 0 TO 15 ;
C_dest : IN INTEGER RANGE 0 TO 15 ;
E1_pos , E2_pos , E3_pos : OUT INTEGER RANGE 1 TO 15 ;
E1_load , E2_load , E3_load : OUT INTEGER RANGE 0 TO 15


Clock Reset and need no introduction . C_orig and C_dest are from the call buttons on each floor . Normally have the value 0 ( inactive) . When a passenger calls the elevator, the floor of origin of the call appears in C_orig , and the desired destination C_dest . Both signals are activated simultaneously , and only one clock cycle .


E1 ... 3_pos are registers that indicate the current position of each lift ( floor number ) . E1 ... 3_load who indicate each elevator is carrying at the time , being 0 when empty , or 1 ... 15 when busy - in this case the number must indicate the floor of origin of the person being transported . These two groups of registers are sufficient for checking the function of our system .


code :
Building control for an elevator ( E1 ), while others stopped. Make him answer calls and take passengers to their destinations , obeying the rules specified


Expand control for the three lifts . Define a logical decision on which lift should meet that call, according to some simple criteria.
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DE2 Ethernet communication

May 6, 2014, 1:13 pm
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hello,
i am new to the world of FPGA and i am currently working on DE2 board.
i have been trying to create a simple program to communicate with my PC via Ethernet.
although I've read a lot about the subject in many forums i can't find a simple example for sending and receiving data via Ethernet.
can anyone pleas try and point me in the right direction?
what should i read and study before jumping into this project?
is it so much complicated then to implement RS232 communication?
can a NOOB like me have a chance in doing so?


any help will be much appreciated!!
thanks to all.
Natan.
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Required Quartus files

May 6, 2014, 2:18 pm
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My system recently crashed. However, before it crashed I had created the schematic of the CPLD I'm going to use and had a clean compile. I save all those files so I didn't have to do the layout again. I can open the project but come up with the message "Can't find design entity "jbe_1sec_timer" which isn't very descriptive. What are the main files I need to be able to reconstruct my previous work? Any suggestions would be helpful. Thanks...
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Error: Can't find the instance. Download a design with SRAM Object File containing t

May 6, 2014, 5:12 pm
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when i perform sigtap ii ,the project don't have any problem before. but recently i add some module to it and use modelsim to simultate it ,then when i perform it again,it shows that "Error: Can't find the instance. Download a design with SRAM Object File containing this instance." what is the problem. i can sure that the .sof file is updated correctly.
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Error: Can't find the instance. Download a design with SRAM Object File containing t

May 6, 2014, 5:33 pm
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when i perform sigtap ii ,the project don't have any problem before. but recently i add some module to it and use modelsim to simultate it ,then when i perform it again,it shows that "Error: Can't find the instance. Download a design with SRAM Object File containing this instance." what is the problem. i can sure that the .sof file is updated correctly.
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Live Control of PWM Outputs (need advice)

May 6, 2014, 10:54 pm
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I've been searching around google for how to implement what I need but I'm not understanding the underlying ideas as a whole, and I'm hoping for some explanation and advice.

My project: Generate several PWM outputs. The frequency/phase/dutycycle should all be controllable WHILE the FPGA is running (if this is even possible?).

My hardware: Altera DE0 Nano board

What I understand so far (I think):
I need to make some sort of live prompt on the screen where the user enters values for the freq/phase/dutycycle. I'm assuming this requires underlying C/C++ to read the keystrokes.
I've written Verilog that uses a counter to turn the PWM outputs on/off according to a duty cycle parameter, as well as a shift register to introduce phase shifting to the outputs.
I don't understand how to use keyboard input or even C/C++ code to change the Verilog module's parameters as the FPGA is running.
The closest thing I can think of is using a NiosII with a C software application, but this would require the user to rebuild and run after every parameter is changed.
Also, I assume there is some sort of Altera IP for PWM outputs, but my searches have given me nothing.


I would really appreciate at least a high level explanation of how one can control Verilog parameters while the FPGA is running and how C code in NIOSII interacts with a Verilog module.

Thank you for any help you can give!
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Pls tell me how to use the NestedLoop1 block in DSP Builder Advcanced Blockset

May 7, 2014, 1:56 am
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Pls tell me how to use the NestedLoop1 block in DSP Builder Advcanced Blockset, a simple model is better.
I do not know where can i put the loop body, how to use the NestedLoop1's terminal.
nestedloop1.jpg
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MegaWizard Generation Error

May 7, 2014, 10:04 am
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PWM signal via sine-triangle comparison

May 7, 2014, 10:08 am
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Hello,
right now i am stuck in aproblem in my project. I hope its not explained to complicated and someone can help me (-:
I try to generate a pwm signal out of a sine with 50 Hz - 20ms.
I have triangle function with a period time of 8 µs by counting from -99 to 99 and vice versa.
I have a sine table with 500 values, so if i want to fit the whole sine into the 20ms period
and i have the triangle with a period of 8µs (400* 20ns) i have to update the sine value every 40µs.
Now i simulated everything and it compiles just fine but i think my design is full of logical errors which i right now cant see.
In the modelsim analysis i see a close pwm signal but with the wrong amplitude, so that the sine function is much larger than the triangle.

I hope someone can help me and thanks in advance for reading through my code!!


Cheers
Tim


Code:
---------------------------------------------------------------------------------
-------------------------Timer Direction Function--------------------------------
---------------------------------------------------------------------------------
TimerDirection:process (CLOCK,RESET,TimerDir,Timer)
begin   
    if  RESET = '0' then
        TimerDir <= '1';
    elsif CLOCK'event and CLOCK ='1' then   
        if (Timer =99) then
            TimerDir <= '0';
        end if;
        if    (Timer =-99) then                       
            TimerDir <= '1';
        end if;
    end if;
end process TimerDirection;
CountingTimer: process (CLOCK,RESET,TimerDir,Timer)           
begin
    if  RESET = '0' then
        --Timer<= (others => '0');
        Timer <= 0;
        countSine <= 0;
    elsif CLOCK'event and CLOCK ='1' then
        if (TimerDir ='1') then                     
            Timer <=Timer + 1;   
        end if;
        if (TimerDir ='0') then                         
            Timer <=Timer - 1;
        end if;
        countSine <= countSine +1;
        if    (countSine = 2000) then                         
            countSine <= 0;
        end if;   
    end if;
end process CountingTimer;


Code:
type table is array (0 to 499) of std_logic_vector(8 downto 0);
function init_table return table is
    variable var: table;
    variable x: real;   
    begin
        for i in 0 to 499 loop   
            x:= SIN(real(i)*MATH_PI/real(500));               
            var(i):=std_logic_vector(to_signed(INTEGER(x*real(100)),9));       
        end loop;   
    return var;                   
end;
constant sinTable : mem := init_mem;
this function generates the pwm signal:
Code:
modulate: process (CLOCK,RESET,TimerDir,Timer)           
begin
    if RESET = '0' then
        PWM_OUTPUT <= '1';               
    elsif CLOCK'event and CLOCK ='1' then       
        if SinValue = std_logic_vector(to_signed(Timer,9))  and  (Timerdir<='1')then       
            PWM_OUTPUT <= '0';
        end if;
        if SinValue = std_logic_vector(to_signed(Timer,9))  and  (Timerdir<='0')then
            PWM_OUTPUT <= '1';
        end if;                                                                                 
    end if;                       
end process modulate;
 
end pwm_process;
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how to link SDRAM with Cyclone FPGA?

May 7, 2014, 11:26 am
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In designig DDR, DDR2, DDR3 DRAM, the data pins and data strobe pins should link to the DQ, DQS, DQM pins. Also the DQ, DQS, DQM pins must be in the same group of the FPGA.

But for SDR DRAM, is there NO such needs, as the design in the sheet 21 of DE2-115 shematic?

Thanks!
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de0 nano to measure temperature of a liquid, greetings from Colombia

May 7, 2014, 12:00 pm
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Hello
I need help with the following project

Temperature Control

- Should survey the temperature of a heat emitting system.
- The temperature signal must be connected to one of the ports A / D of nano-DE0
- The Deo-nano must control a fan that reduces temperature heat emitting system
- In 2 7 Segment displays (or LCD display) should displaying the temperature value.
- Through the switches (or external keyboard) should set the desired temperature.
- To observe the desired temperature and the actual temperature of system must press a button to select the
temperature to observe.





Thermocouple what can I use?
ideas, suggestions



perdon por mi ingles, traducido por https://translate.google.com/

Gracias de antemano
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Can't get Qsys to generate a testbench for a custom component using exported signals

May 7, 2014, 4:36 pm
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I’m trying to use Qsys 13.1 to generate a testbench for a custom component that uses one Avalon Slave interface and one conduit to export 4 signals. I know the component works, I use it in an existing design, I'm just trying to come up to speed on Qsys generated test benches.

I add my component as the sole component in a new Qsys system and export all the interfaces (clk, reset, avalon_save, conduit).

When I generate the testbench it throws an error “Error: TB_Gen: Design has 4 but instance has 0 exported interface”

If this worked, I thought it would attach an Altera Conduit BFM to the conduit interface of my component in the generated test bench.With that assumption, I tried piecing together the test bench by hand but when I connect the Conduit BFM to my conduit_end interface, it complains that they need to be on the same clock and reset domain, but the Conduit BFM doesn’t have a clock or reset interface.



This seems like a simple thing that most everybody using a testbench would want to do frequently.The only tutorials that I’ve found use a FIFO or some other Altera component as a DUT which doesn’t export any signals.



Can anyone point me to an example that could enlighten me on this subject?

Thanks for your time!

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std_logic_vector won't accept certain values

May 7, 2014, 10:32 pm
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I was asked to design a simple can dispensing machine using VHDL.I have an input called CoinIn and is defined as an std_logic_vector(1 downto 0);for some reason, when I try to force it with a "11" it will treat it as a "01" and when i try to force it with a "10" it will treat it at "00" (meaning that the CoinIn[0] is always connected to ground) .Does anyone have any idea what the problem might be?(I use Modelsim Student Edition for simulating)
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I recieve "cant find port in design".

May 7, 2014, 10:34 pm
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hi;
when simulating my design in Quartus I recieve "cant find port <name> in design.
alteras help said:
CAUSE: You specified a node in the vector source file, but the Quartus II software cannot find the specified port in the top level design in the current Quartus II project.
ACTION: Either remove the node from the Waveform Editor, or change the name, width, or direction of the port to match a similar port in the top level design.
but this didnt help me.
what should I do?
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How do I add interrupt-names parameter to the device tree?

May 8, 2014, 2:06 am
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I'm trying to use mSGDMA and am looking at the interrupt-names field in the device-tree-source of the gmac and see this:

hps_0_gmac0: ethernet@0xff700000 {
compatible = "synopsys,dwmac-1.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
reg = < 0xFF700000 0x00002000 >;
interrupt-parent = < &hps_0_arm_gic_0 >;
interrupts = < 0 115 4 >;
interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */
mac-address = "[00 00 00 00 00 00]"; /* embeddedsw.dts.params.mac-address type STRING */
address-bits = < 48 >;
max-frame-size = < 1518 >;
local-mac-address = [ 00 00 00 00 00 00 ];
clock-names = "stmmaceth"; /* appended from boardinfo */
clocks = < &emac0_clk >; /* appended from boardinfo */
status = "disabled"; /* appended from boardinfo */
}; //end ethernet@0xff700000 (hps_0_gmac0)


which appears to allow the device driver to call platform_get_irq_byname with the specified name. How can I get a name that I can use with platform_get_irq_byname into the device-tree, short of editing it by hand?



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Accessing image stored in SDRAM sent through PCIex from Intel Atom host on DE2i-150

May 8, 2014, 3:33 am
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Hi all, i am currently working on hardware accelerator for a gesture recognition application on DE2i-150.
Hope there is anyone can help me on my problems written below.

I have successfully sent webcam image(640x480x3bytes) to SDRAM in FPGA through PCI express (Avalon Memory mapping). I wish to do some image processing on the image stored in SDRAM. However, i have no idea how to access the data stored in SDRAM. I am using QSYS components now as the PCI ex has to be done there. Is there any Qsys component that can act as SDRAM controller which allows me to access the data ??
qsys_image_simple.JPG
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