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Weird problem with Fifoed-UART

August 25, 2014, 4:09 am
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I am experiencing problems with Fifoed-Uart, first I have tried the latest version (v13.1) and I have seen that it is not generating RX-FIFOs (I inspected the verilog files, TX-FIFOs are there, but RX-FIFOs are missing), I think it is caused by a typing error in pm file named: "em_fifoed_uart_qsys.pm"

...
#enw for fifoed uart
$use_tx_fifo = $Options->{use_tx_fifo};
$use_rx_fifo = $use_rx_fifo;
$hw_cts = $Options->{hw_cts};
$trans_pin = $Options->{trans_pin};
$fifo_size_tx = $Options->{fifo_size_tx};
$fifo_size_rx = $Options->{fifo_size_rx};
...

I think the line "$use_rx_fifo = $use_rx_fifo;" has a typing error, but when I changed it as "$use_rx_fifo = $Options->{use_rx_fifo};", I cannot make qsys generate the files. It freezes while creating the files.

After that I managed to use an earlier version (v9.3.1), everything seems fine with this one but I cannot receive first 63 chars somehow after starting up. 64th char and the following chars are OK. The first 63 chars disappear and 64th char is received like it is the first char received. But the system is all OK after that if you don't mind about this lost data.

My project is designed for communicating with MODBUS/RTU nodes (RS-485) and I am using Quartus II 64bit v13.1. So it is not possible to waste these 63 chars received in the start-up since it includes data related with a request.

My question is: Is it possible to modify some code to make fifoed-UART think that it has received 63 chars or something like that ?

Extra Info: My fifos are 256 Words (with memory elements) for both Tx and Rx, using 4 char periods Rx Timeout, fixed baudrate 9600, using the pin transmitting with MAX485.
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TSE without internal FIFOs

August 25, 2014, 5:14 am
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Hi

I would like to take the internal FIFOs from the tse-IP external....(for using timestamping in future)

But somehow I can't get it running. I've added the qsys and my toplevel, maybe one of you can see an error in the configurations (FIFO, DMA)

I especially don't know how to configure my FIFOs. I tried to increas the size, but it didn't help.
Attached Files
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Indirect configuration

August 25, 2014, 6:07 am
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I work with Cyclone V E and choose Indirect Configuration solution ( .jic ). AS 4X
Now I have : 90% (Failed), also there are no signals on my EPCQ32 pins.
Programming into RAM was successful (.sof)

May be I find a mistake in MSELs. I choose wrong conbination, because I thought that is just JTAG configuration.
00000 instead 10010
What can I do now? How can I find out real problem with experiment? Should signals be on EPCQ pins even with wrong MSELs?
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Gate Logic missing in my Symbol Editor?

August 25, 2014, 6:20 am
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Hi,

I generated a qsys setup. Now I would like to edit the generated .bsf with the symbol editor. After that, I want to add it to my project. I went File -> Open... here, I navigated to my component: ./soc/soc.bsf, then clicked on it. The block/symbol editor opened automatically (is there actually a menu item for it?) on the component. Just the component. Nothing attached. In the editor I see, I don't have no AND gate icon in the small icon list. It's simply missing. Anyway, there is no way of connecting two pins with e.g. a logic NOR gate which I actually need to do. I did this like months ago in another Quartus2 13.1 setup, but here it seems to be missing / not available.

Q: What am I doing wrong? How may can I set a logic NOR gate?

System: quartus II 13.1 (web), Linux Debian
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Browser Input / Output Error

August 25, 2014, 6:40 am
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Hi,

When I try to search some text in the upper right textfield of my Quartus II/13.1 (on Linux Debian), a small dialog opens "Input/Output Error"
on the shell the follwoing text appears. Actually Quartus is running in a VM via NAT, but a browser inside the VM works and does not need any proxy settings.
Code:
$ quartus --64bit
XPCOMGlueLoad error for file /usr/lib/xulrunner-24.0/libxul.so:
/opt/altera/13.1/quartus/linux64/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/xulrunner-24.0/libxul.so)
Couldn't load XPCOM.
Q: How to fix this?
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How to handle complex external signals in Qsys

August 25, 2014, 7:29 am
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It seems that in Qsys, it is not possible to export any signal that is not STD_LOGIC or STD_LOGIC_VECTOR (or a SUBTYPE thereof). Is this correct ?

We have a slave that exports a bunch of these in a RECORD, to minimize the coding effort (and risk of making errors) to connect them to other subsystems in the FPGA. There's a post on this forum back in 2009 where this was already discussed for SOPC Builder and the suggestions was to use a function to mux/demux these signals to SL(V)s and back. Before embarking on this journey, I'd like to make sure I haven't overlooked anything.

Thanks,

J.
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OpenCL on SoCKit

August 25, 2014, 11:02 am
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The results I'm getting are different than others that I'm seeing. I'm following the steps in the Getting Started Guide:

I can verify the installation with:
~/altera$ aocl version
aocl 14.0.200 (Altera SDK for OpenCL, Version 14.0 Build 200, Copyright (C) 2014 Altera Corporation)

I can see the board packages:
~/altera$ aoc --list-boards
Board list:
c5soc
c5soc_sharedonly

But if I try to install the FPGA board:
~/altera$ aocl install
--------------------------------------------------------------------
No board installation routine supplied.
Please consult your board manufacturer's documentation or support
team for information on how to properly install your board.
--------------------------------------------------------------------

And if I run diagnostics:
~/altera$ aocl diagnostic
aocl diagnose: Running diagnostic from /home/ghelbig/altera/14.0/hld/board/c5soc/arm32/bin
/home/ghelbig/altera/14.0/hld/board/c5soc/arm32/bin/diagnostic: 1: /home/ghelbig/altera/14.0/hld/board/c5soc/arm32/bin/diagnostic: Syntax error: word unexpected (expecting ")")
aocl diagnose: failed.


Any pointers on where to look?
Regards,
Gary.
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New to VHDL, problem with variables/signal?

August 25, 2014, 1:28 pm
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I am new to VHDL but trying to learn. I would like to make an alarm clock, i decided to start with a mux, 4bit wide 2 to 1. I am using the DE1 board, for testing i want to conect the mux to the switches and show the output on the green leds based on the selector switch. I think that my problem is somehting with the variable scope. can anyone offer any input on the following code?

The error i get right now is:
Error (10482): VHDL error at Lab1.vhd(49): object "S" is used but not declared
Error (10482): VHDL error at Lab1.vhd(47): object "S" is used but not declared

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY lab1 IS
    PORT (
        SW :  IN STD_LOGIC_VECTOR(9 DOWNTO 0);
        HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6);
        LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
        LEDG : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
        );
    END lab1;

ARCHITECTURE Behavior OF lab1 IS
    COMPONENT mux4bit2to1
        PORT (
            A, B, C, D : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --MUX Inputs
            W, X, Y, Z : OUT STD_LOGIC; --MUX Outputs
            S : IN STD_LOGIC --Selector bit
        );
    END COMPONENT;
   
    COMPONENT char7seg
        PORT (
            N : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            Display : OUT STD_LOGIC_VECTOR(0 TO 6)
        );
    END COMPONENT;
   
    BEGIN

    mux1 : mux4bit2to1 port map(
        A(0) => SW(0),
        A(1) => SW(5),
        B(0) => SW(1),
        B(1) => SW(6),
        C(0) => SW(2),
        C(1) => SW(7),
        D(0) => SW(3),
        D(1) => SW(8),
        W  => LEDG(0),
        X  => LEDG(1),
        Y  => LEDG(2),
        Z  => LEDG(3),
        S  => SW(9)
    );

    muxselect: PROCESS (S)
    BEGIN
        case S is
            when '0' =>
            W <= A(0);
            X <= B(0);
            Y <= C(0);
            Z <= D(0);
            when '1' =>
            W <= A(1);
            X <= B(1);
            Y <= C(1);
            Z <= D(1);
            when OTHERS =>
            W <= '0';
            X <= '0';
            Y <= '0';
            Z <= '0';
        END CASE;
    END PROCESS;
           
           
    LEDR <= SW;

END Behavior;
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Trouble Getting DDR SDRAM Working in Qsys

August 25, 2014, 2:28 pm
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Hello,

I'm making a board with a Cyclone IV FPGA, and having some trouble getting my DDR signals to be what they should be. I have a clock bridge between a Nios II Processor and my DDR SDRAM controller with ALTMEMPHY. When I probe the nCS signal it appears to be stuck high. When I program it, it may drop low for a few clock cycles, but that's it. DQ pins are stuck low. I'm thinking maybe it's stuck in reset, but I tried exporting both reset_n signals, forced them to '1' and I still get the same issue. My refclk is 10MHz, and I know that works. Should the DQ pins or nCS be switching values if it's working correctly without nios running on it? I'm trying to download my .elf but since the DDR doesn't seem to be working, I can't get the instructions/data in there. If anyone has an idea to try, it would really help me out!

Thanks,
- Rob
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Problem with yocto build

August 25, 2014, 11:54 am
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I have tried to build using poky an image for the SoC, I am running a VM with 12.04 LTS on a 14.04.5 LTS host.
no matter waht I do I get the following eror.Looking around I have found to sites with builds bot both result in the same failure.

Can someone point out th eissue ?

thanks


ERROR: Task 47 (/home/sedev/yocto/meta/recipes-devtools/libtool/libtool-native_2.4.2.bb, do_configure) failed with exit code '1'
NOTE: Tasks Summary: Attempted 48 tasks of which 47 didn't need to be rerun and 1 failed.
No currently running tasks (39 of 63)

Summary: 1 task failed:
/home/sedev/yocto/meta/recipes-devtools/libtool/libtool-native_2.4.2.bb, do_configure
Summary: There was 1 WARNING message shown.
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
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Arrow SoCKit FPGA-to-HPS SDRAM (f2h_sdram) Help Needed!

August 25, 2014, 5:15 pm
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Hello All!

I've been visiting this forum daily and, for the most part, finding answers to my questions. However, I've finally gotten to a point in my project hat I have no idea what I'm doing!

As a precursor, you should know that I'm a young engineer and I really do have very little experience using Altera products and coding linux drivers. But that is why I'm here -- to learn!

Also, I've successfully followed a nice tutorial by Zhemao (?) for using the lightweight HPS-to-FPGA bridge to control FPGA I/O, but I now need to understand how to use HPS DDR3 memory and how to access the HPS memory from the FPGA. I have read through this tutorial, but I am looking for something a bit more in depth (step-by-step) from start to finish, if you will. Just a simple example (as described below).

I don't like to sell myself short, but... I've seen several examples on this forum and I really do need a dumbed-down, step-by-step guide of creating a very simple design (Qsys/Linux driver). Perhaps a simple example of taking a push button output (an HPS button?), storing it in DDR3 memory, and turning on an FPGA led...? That way I can begin to understand both the device driver, the Qsys, the Quartus, and the pin-layout aspects of dealing with DDR3 and f2h_sdram (possibly with the address span extender). As mentioned, I am using the Arrow SoCKit -- it has the Cyclone V 5CSXFC6D6F31C8 SoC. Any and all help is needed! (Even if it is just pointing me to other posts that I've already read.)

Note: For those who are interested, here's my ultimate project goal that I need to accomplish once I understand how to utilize DDR3... Recieve streaming video over ethernet (at giga-bit rate) through the HPS and store in DDR3 SDRAM; read the stored video from the FPGA (f2h_sdram0?) and perform predefined video processing; push the processed data back to the HPS (f2h_sdram1?) where further processing will be performed (tracking, etc.). If any one has better design ideas, feel free to share (in a PM preferably).
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Cyclone V GX 5CGXFC5C6F27C7N is not recognized in ubuntu 14.04

August 25, 2014, 7:53 pm
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Hello all,

I have a Cyclone V GX starter kit (5CGXFC5C6F27C7N) board, and I am trying to program it using Ubuntu 14.04. I already compiled the code and it does not have any error. However, when I open the "programmer" application (tools->programmer), my device is not recognized.
I clicked the "hardware setup" button and the only option I can choose is USB-Blaster variant 2-1.

When I plug it using windows 7, it does not have any problem. So, I wonder if ubuntu 14.04 is not ready for this board :cry:

Do you know what can I do to get my board recognized so I can program it?:confused:

does not recognized.jpg Option_hardwaresetup.jpg

I would appreciate your help, and if you need further details, please let me know.

Thanks in advance for the help on this.
Attached Images
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Bad placement result from Quartus 13.1.0 and How to work around?

August 25, 2014, 8:49 pm
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Hello All,

I am using Quartus 13.1.0 64-bit version. I think I got an example of bad placement result. And I want to know how I can resolve this (say, by using some kind of constraint)?

In my case, TimeQuest reported timing violations for a path, which is from logic to block memories. And when I examine the graphical data path, I see that Quartus has placed the memory too far away from the logic. (see my attached image 1).

This is confirmed when I examine delay of each stage of data path. I can see that the interconnect delay (IC) connecting the logic to the memory is 2.460 ns (too large!). (see my attached image 2)

So I would say this is probably a bad placement.

Then my question is: how can I resolve this (say, by using some kind of constraint)?

Thanks.

quartus_long_interconnect_delay_1.jpg
quartus_long_interconnect_delay_2.jpg
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generate UDP or IP broadcast

August 25, 2014, 11:54 pm
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Hi


I have a Nios on my CycloneVGT running with the Altera TSE and the SimpleSocketServer. But it don't work properly since took the FIFOs external in the TSE.


I would like to have a constant stream of some well-defined packets, which are sent from the nios. This way I can look all the different steps in my system where it gets failed...


How can I generate some packets?


I found the function "ip_write" which seems to fit exactly my problem. But how do I generate a packet? I'm not very used to C++...
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backward compatibility of Quartus 13.1 - 64 bit

August 25, 2014, 11:59 pm
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Hi,
Is Quaturs 13.1 64 but version is backward compatible with Quartus 12.1 32 bit version?
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Pulse signal into FPGA issue

August 26, 2014, 12:04 am
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There are several pulse signals will be input into FPGA through normal I/O pins. These pulse signals are generated with fast rising edge. My question is what effect will be when they go into fpga through normal I/O pins? Will the rising edge become slower? And how to ensure their primary property without any change?
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Nios as slave with spi

August 26, 2014, 1:20 am
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Hello guys, I'm writing beacause I need some suggestions..

I have an FPGA running a NIOS2 processor. This processor will be interrogated by a master peripheral with the SPI protocol. I know that it's possible to configure the SPI with a software interrupt.

By the way I'm not sure about how configuring the SPI peripheral as slave. Actually I receive some strings with different lengths from the master system, than I have to extrapolate the informations contained in these strings, do some elaboration and finally send the answer message if needed (that are other strings with different lenghts).

Sumnmarizing I need to read the string sent by the host then have enaugh time to elaborate the information and finally send the answer message.

So I thought to enable the interrupt on the SPI and get the string from the master, when the string is received set a register to 0. Now the master must poll the register until goes to 1 before give me the clock necessary to have the answer message transmitted.

How can I do the "register thing" ? There are better options ?



[EDIT]
One more thing.. I saw that the SPI has a fixed bitsize, so if I have to receive a string with a non fixed length how can I manage the SPI configuration ?
I want to accomplish something like this
figure2.jpg
in which the length of the bitstream is only defined by the edge of the SSN.
Attached Images
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ALTLVDS_RX behavior on Quartus II 13.1 and Quartus 14.0

August 26, 2014, 2:20 am
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Hi all,

I'm using ALTLVDS_RX Megafunction to interface CameraLink device.
I have no problem as long as I compiled with Quartus II 13.1 version. When I wanted to compile with the 14.0 version, the compilation was successfully finished but the output data alignement was be changed. I didn't change megafuction settings.
I don't have succeded to get the same alignment (trying to change phase shift alignment in the megawizard or in ALTLVDS_RX variation file).


Is there anyone knows how to fix this problem?

Hery
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Missing report after change to AOCL version 14.0

August 26, 2014, 4:46 am
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Hi all,
after changing from version 13.1 to 14.0 the aoc optmization report is missing.
Only the resource usage is given back with the paramter --report.



aoc --report -c -v -g test.cl
aoc: Environment checks are completed successfully.
aoc: Selected target board pcie385n_a7
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 19% ;
; Dedicated logic registers ; 8% ;
; Memory blocks ; 18% ;
; DSP blocks ; 0% ;
+----------------------------------------+---------------------------;
aoc: First stage compilation completed successfully.
aoc: To compile this project, run "aoc test.aoco"


To make shure that it is not dependant on the kernel code I also used the example from the Best Practices Guide Page 1-31.
But it is the same with arbitrary code.
#define N 128
__kernel void unoptimized (__global int * restrict A,
__global int * restrict B,
__global int* restrict result)
{
int sum = 0;
for (unsigned i = 0; i < N; i++) {
for (unsigned j = 0; j < N; j++) {
sum += A[i*N+j];
}
sum += B[i];
}
* result = sum;
}
Can you help me?
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125 MHz clock enable in Arria V

August 26, 2014, 5:49 am
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Hi!

I'm working with an Arria V GT Development kit and I cannot see where the clocks are. I only find the USB, the enet and a 50MHz clock, but there are more oscillators in the board and I don't know how to activate them.

I checked the DIP Switch at the bottom of the board and it's on. I also checked the other input clock signals and no other clock signals appeared. According to the manual, it's the MAX II that enables the 125 MHz clock, but I have another problem with this because I had to upgrade to quartus 13.0 because quartus 12 doesn't support the Opencores plus (as far as I can remember), so now I cannot check the clocks with the clock control because the quartus version is higher than the development kit.

Does any of you have an idea of how to enable those oscillators? The only two ideas that I have are either reinstalling again quartus 12 or programming somehow the MAX (I'm not so experienced in this), but I'm not even sure that I can get anything out of that.

Thanks in advance
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