Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Cyclone III asynchronous input signal synchroinization problem.

August 26, 2014, 6:00 am
$
0
0
Hello. I have a problem with the asynchronous input signal synchronization. I am trying to make the IIC_Slave based on Cyclone III FPGA Starter Kit. Altera Quartus II 13.1.0 x64
I saw 3 cases:

  1. If I not use synchronization triggers, I can enjoy by metastable clock control that affects as a number of pos- and neg- edges in each clock front. It is shown at pic 1.
  2. If I use the synchronization triggers, this number of fronts is disappear (as expected) but a new bug is appeared (it look’s like a reset signal on some negedges of the clock signal). At the same time the reset signal are not detected by oscilloscope.
  3. If I use the case 2 conditions with the SignalTap generated module all works correct! But it is not a valid possibility to solve problems. (738 logic elements and 41000 memory bits are wasted)


Oscillograms and verilog file are attached. Here are explanations for the oscillograms.
The digital signal D7 – reset for the counter. The digital signals D6-D1 – bits of the shift counter. The yellow analog signal – data line from IIC. The green analog signal – clock line from IIC.
Please tell me if you have any idea about this situation. I am trying to make it works about a week and have a strong headache. I can’t even formulate a appropriate question for google.
Attached Files
↧
Search

irda problem

August 26, 2014, 7:09 am
$
0
0
Hi, i'm trying to implement an IR interface with FPGA altera de2, cyclone ii.
the IRDA ic is hsdl-3201.

after looking with osciloscope, i realized that ir signal is modulated by 38khz pulse (with D.C about 90%)
so i have built a clock with frequency ~38khz , so sampling at this rate to generate demodulated signal.

after that, try to read the trasmit data and count the time the signal is high and low. it doesn't work
and i guess there's something basic i don't do /understand.
could someone advice plz.
↧
↧

FPGA-to-HPS SDRAM vs. HPS-to-FPGA

August 26, 2014, 8:15 am
$
0
0
I'm a relatively new EE (about 5 years EE experience), but I have only a few months of hardware design. I have a design question that I'm hoping someone can shed some light on, teach me a little :-)

I'm taking video in over gigabit ethernet. I will run some video processing on it (on the FPGA fabric) and then pass the processed video to the HPS to be further processed (tracking, etc.). My questions are as follows... because the gigabit ethernet comes in on the HPS side,

(1) would it be best to store the video in HPS DDR3 then access it using the FPGA-to-HPS SDRAM interface, or
(2) pass the video over the HPS-to-FPGA bridge and store it as FPGA DDR3, thus freeing up the HPS SDRAM for other uses?

Thank you.
↧

Count_Binary alt_u8 not found

August 26, 2014, 12:45 pm
$
0
0
I have a simple NIOS II/s running the count_binary example. Eclipse is used as installed by Altera. The problem I'm running into is if you start a new project and select count_binary everything is fine. However, when you quit Eclipse and start it up again, the count_binary.c file shows errors. It cannot find alt_u8 is one error. There are several all related to libraries. I check the properties of the count_binary.c and the path is there. It only happens when you quit Eclipse and then start it up again. Why does it find the libraries only when you create a new project and never again? Any idea as to what is wrong?
↧

Ver. 14.0 aoc -march=emulator Option not working (Windows 7 with Bittware Board)

August 26, 2014, 2:17 pm
$
0
0
I have been able to get the -march=emulator option to work in the sense that the compilation process completes without an explicit error and produces the corresponding .aocx file. However, when I attempt to load and create an OpenCL program from the .aocx file (calling a method from the AOCL_Utils.cpp) I get an OpenCL run-time error = -42 which is CL_INVALID_BINARY.

Here is the line that fails in the Vector Addition Example:
program = createProgramFromBinary(context, binary_file.c_str(), device, num_devices);

Below is the kernel code:
__attribute ((task))
__kernel void vectorAdd(__global const float * restrict x, __global const float *restrict y, __global float *restrict z)
{
// get index of the work item
int index = get_global_id(0);

// add the vector elements
z[index] = x[index] + y[index];
}

And here is the aoc command I am using along with the output:
>aoc -v -march=emulator vectorAdd.cl
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected target board s5phq_d5
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling for Emulation ....
aoc: Emulator Compilation completed successfully.
Emulator flow is successful.

I'll also add that the board diagnostics are working fine; I'm running Windows Visual Studio 2013 Professional, my environment is setup using
> vcvars64.bat
And I am running the console with Admin rights.

To help troubleshoot further, I have re-installed Windows Visual Studio 2013, the Altera Quartus software, and the updated BSP from Bittware, etc., along with numerous restarts, all of the diagnostics work and I am able to produce a correctly functioning .aocx file when performing a full hardware build.

Any ideas / suggestions?

Thanks!
↧
↧

NIOSII with EP2C8Q144 ?

August 26, 2014, 2:43 pm
$
0
0
Guys,

Is it possible for me using NIOSII with EP2C8Q144 ?

Thanks
↧

Multiple Thread with Altera OpenCL

August 26, 2014, 7:27 pm
$
0
0
Altera SDK for OpenCL Programming Guide claims:

Quote:

The Altera Software Development Kit (SDK) for OpenCL (AOCL) host library is not thread-safe.


I have a simple question.
In this context, what "not thread-safe" means strictly?


  • Only main thread is allowed to call OpenCL API.
  • Only one thread is allowed to call OpenCL API.
  • Multiple thread can work only if there are appropriate exclusive lock not to call OpenCL API simultaneously.


Anybody knows ?

iitaku
↧

Altera Cyclone V development board FPGA problem (error code:-4)

August 26, 2014, 10:08 pm
$
0
0
I am working on the Altera Cyclone V Development board (revision D).
It seems that the FPGA image is not loaded after power up. I found following lines in the uboot bootlog:

reading soc_system.rbf
7007184 bytes read in 2368 ms (2.8 MiB/s)
altera_load: Failed with error code -4

My board switch and jumper settings are listed as below:

SW1 All OFF
SW2 All OFF
SW3 1:ON 2:ON 3:ON 4:ON 5:ON 6:ON
SW4 1:OFF 2:OFF 3:ON 4:ON

J5 open
J6 shorted
J7 shorted
J9 open
J13 shorted
J16 open
J26 right shorted
J27 right shorted
J28 right shorted
J29 right shorted
J30 left shorted
J31 shorted


Please help
↧
Search

avalon-mm cyclone V PCIe with NIOS II

August 27, 2014, 2:00 am
$
0
0
Hi,

I have developed a design that implements a PCI express rootport with a Cyclone V GX connected with a NIOS II processor connected via Avalon bus. Is there any example that implements basic init operations from NIOS II processor to access CRA register, send/read TLPs.... Thanks.




Adolfo
↧
↧

i want to use high performance controller ii ,but is puzzled by local_burstbegin??

August 27, 2014, 2:08 am
$
0
0
dd1.JPG
need help please
i will use the high performance controller ii directly ,and will not use sopc
i have noticed that the hpcii example uses the signal of local_burstbegin ,local_write_req and local_ready to implement burst write data to DDR2,and firstly there is local_burstbegin of one clk(i understand this burstbegin is to prepare for the really burst operation next), then wait for serial clk( is the number is fixed to wait for 6 clk ??，because i count in the wave ,and there are 6 clk , but i can not find speciation anywhere ) ,and again the local_burstbegin ,local_write_req is given (on the same time ,the local_ready signal is asserted),and on the same time the beginning address and data is given on the bus,and the burst write is complete

my questions :1) how many clk should wait for between the prepare local_burstbegin and the next realy write local_burstbegin,i can not find speciation anywhere ,and i count the wave figure to get the wait number of clk ,that is 6 clk ,is it right ??
2) is this the standard operation mode for every burst write??
3) if i want to write 64 byte ,how can i use the burst mode?(such as the ddr2 data width is dq = 8bit,and burst length is 4 ) ? i need two burst to complete the 64byte write, should i give the firstly prepare local_burstbegin of one clk when i carry on the second burst operation？
Attached Images
↧

How to create bootable VxWorks SD-Card?

August 27, 2014, 2:11 am
$
0
0
Hey!

I'm very new in this topic and i read a lot to come into it. But i still have some problems.
I have a Arrow SoCkit Cyclone V Board and the goal is, to get a working VxWorks System on it.

I already created a bootloader, that works and i can execute the standard u-boot commands. Now i tried to get the Bootrom of VxWorks started, as I read in a few documentaries and forum posts. But it didn't work yet. I tried to copy the bootrom to a certain adress or to a seperate FAT partition (with a modified bootloader). But it didn't start.

Did I forget something or understand something wrong?
I hope you can help me.

Regards
Kille
↧

Why throughput estimation deprecated in V14.0?

August 27, 2014, 4:15 am
$
0
0
Hi all,

i found out in documentation (Altera SDK for OpenCL Version 14.0 Release Notes) that the throughput estimation deprecated?
Can anybod say why? It was a good, nice and helpful tool!
↧

DE2-115 generate serial number from ethernet MAC address (NIOS II)

August 27, 2014, 6:43 am
$
0
0
What I'm trying to achieve is a serial number that does not get wiped when the DE2-115 is re-programmed or powered off.

The on-board SDRAM and SRAM require a voltage, so the serial wouldn't persist after a power down, and the flash is used for the NIOS system so I can't use that (unless someone knows how to partition off a byte or two that wouldn't get overwritten when flashing the NIOS???).

What I was wondering was: is there a way to read the MAC address from one of the two Marvell 88E1111 Ethernet PHY chips? This could then be used to generate a unique serial number within the NIOS.

The ethernet connections are completely unused and unimplemented in the design, and if possible I don't really want to implement a whole ethernet interface just to get a MAC address.

Is this possible? Or is there an easier way to achieve a persistent serial number on a DE2-115?
↧
↧

simulation with modelsim after quartus II vhdl design

August 27, 2014, 8:19 am
$
0
0
Hi,

I have been wanting to verify the correct operation of my vhdl design file in quartus II (to be used on a caen v1495 VME board).
I have succesfully compiled the quartus II project with the vhdl files. and then I clicked on the "RTL simulation" button to launch the modelsim software.
I then simulated my current work directory and design file. After which I added 2 input signals that are required to produce an output. However how do I view or add the resultant output waveform to the wave window, so that I can test for the correct logic operations given the inputs and outputs.
Thanks in advance.

Kind regards.
↧

How do you import a .vqm from Synplify?

August 27, 2014, 12:51 pm
$
0
0
I use Synplify Pro for the synthesis. How do you import this file into Quartus GUI? Do you delete the .vhd file? There is absolutely no information or examples that show this on the Internet. I have one .vhd file and removed it. I added the .vqm file to the project. Is that "importing" the VQM? Sure it compiled P-R. How do I know the .vqm was used? I never saw the .vqm file listed in the messages. If Synplify synthisizes the code why does Quartus synthisze again? At least that's what I read. There is no straight forward explanation that explains for example: 1) Synplify will synthesize your .vhd files. 2) Quartus will take that output and do this or that. The Altera literature I've read is rather confusing regarding 3rd party tools. Thanks
↧
Search

JTAG Header for HPS and FPGA

August 27, 2014, 1:39 pm
$
0
0
Hello, I would like to use one JTAG header for the FPGA side and one header for the HPS side of the side will this be a problem? I thought this would make this less complex. My co-worker daisy-chained the JTAG with the FPGA being first in the chain and then the HPS. I've looked at the documentation but haven't found an example of using a separate header. Can anyone help?

Thanks,
joe
↧

Timequest for beginers

August 27, 2014, 6:58 pm
$
0
0
Hi,

I'm involved in an international open source Software Defined Radio project that uses Altera FPGAs (www.openHPSDR.org). We are currently encouraging our members to contribute to FPGA development.

Many of our members are very experienced C/C++/C# programmers but have not been exposed to FPGA coding before. One issue we find is the steep learning curve for such programmers when starting to use Timequest.

In which case we have written a user guide, aimed at beginners, called "A standardized procedure for closing timing on openHPSDR FPGA firmware designs".

You can obtain a copy of the document here:

http://www.k5so.com/TimingClosureFieldGuide.pdf

We would welcome peer reviews by experienced Timequest users in order to continually improve this document.

Regards

philh
↧
↧

Random number generation and indexing into RAM/ROM block

August 28, 2014, 8:00 am
$
0
0
Altera Gurus,

I am developing a random pulse generator based on certain external inputs. The pulse generator will be implemented on a Cyclone III device and coded in VHDL using Quartus. The amplitude of these pulses are controlled by an external amplitude spectra. This will be stored in .mif files which will be used to initialize ROM/RAM blocks. I have implemented a 2^16 pseudo-random number generator based on the LFSR method. These random numbers map to a certain amplitude. These mappings are stored in the .mif file. The mapping is many-to-one; many random numbers map to the same amplitude. An example is shown below to explain the logic:

x[0] = 1
x[1] = 5
x[2] = 10

In my code, if I generate a random number between 1 and 5, then my amplitude will be 1. Similarly if a random number is generated between 5 and 10, the amplitude will be 2. So the amplitude is the index+1. I am having trouble implementing this logic in VHDL. It's not a true ROM/RAM in the sense that the "address" being input to the ROM/RAM block is not the index, but is used to determine the index. For now I have for-loop which basically runs through the entire array, compares the random number to the values in the array, and outputs the index. However, Quartus will no longer synthesize a ROM/RAM block with this logic. Plus I would have to declare a massive constant array (256 values) to implement this since I didn't see a way to initialize a constant array from a .mif file.

Any ideas/thoughts as to how I can implement this logic by using RAM/ROM blocks and for-loops?
I've drawn a crude picture of what I want to implement.

implementation.jpg
Attached Images
↧

Cyclone III Reset with unrelated HV pulses

August 28, 2014, 9:40 am
$
0
0
Hi All,

I have a cyclone III that I am using to filter and process a digitized waveform created from an attenuated high voltage source on the same board. The board takes in up to 15kV and attenuates it down to <1V for digitization by an ADC, where the signals are sent to the CIII and filtered and processed for export to a microcontroller. The design works fine at lower analog input pulses, up to ~4kV, however above this point my FPGA seems to go into configuration mode and all of my outputs go high (I imagine they are being tristated and then the pull-up resistors bring the signals up to my 3.3V). Can anyone give me some guidance as to what circumstances would put my FPGA back into configuration mode? When I bring the input pulses back down to below the ~4kV threshold the EPCS4 reconfigures my FPGA and it works fine again.

Thanks for any help!
↧

Using Stratix V Transceiver native PHY core in the place of Arriai V PHY core

August 28, 2014, 10:03 am
$
0
0
Hi All,
Is it possible to directly replace the Transceiver native PHY core of Arria V GZ with Stratix V Transceiver native PHY core? If so how can it be implemented. Though its been stated Arria V GZ supports only maximum of 9.9Gbps Standard PCS it can be further extended with Stratix IP to 12.5 Gbps. I tried manually instantiating the IP and synthesize was successful whereas the fitter found error stating that the output frequency exceeds that of the current device grade's maximum.

Thanks inadvance
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>