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Error while generating DDR2 IP core for CycloneIV in Quartus13.1

October 6, 2014, 10:40 pm
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Hi all,
Can anybody help me out to remove the following error I am getting while generating the core.
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Error (332000): can't read "dqsclksource": no such variable
while executing
"create_generated_clock -multiply_by 1 -source $dqsclksource -master_clock $dqsclksource $dqspin -name $dqs_out_clockname -add"
(procedure "add_requirements_for_instance" line 263)
invoked from within
"add_requirements_for_instance $corename $inst t board ISI $DDR2_USB_phy_use_flexible_timing"
("foreach" body line 3)
invoked from within
"foreach inst $instance_list {
post_sdc_message info "Adding SDC requirements for $corename instance $inst"
add_requirements_for_instance $corename $..."
(file "DDR2_USB_phy_ddr_timing.sdc" line 635)
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If I comment those lines in .sdc file, I am getting similar errors for other variables.

Thanks in advance.
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Having trouble with the alt_spi_is_ready() function

October 7, 2014, 12:34 am
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Hi,

I've been trying to control a simple SPI LED driver IC using the SPIM0 unit in my cyclone V HPS.
The problem is that the alt_spi_is_ready() function doesn't do what I expect it to do.

Before initiating a write, my software first calls alt_spi_is_ready() to see if the SPI unit is busy.
However, that function always returns 'false', even if the SPI unit is still transferring data.
This causes my software to continue writing new words to the SPI unit, causing the previous transfer to be corrupted.

I've looked at the Altera-SoCFPGA-HardwareLib-SPI-RW-CV-GNU example code and this project uses alt_spi_is_ready() too.
So what am I doing wrong? Has anyone gotten the HPS SPI unit to work properly? I'd like to know.
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MAXV - User Flash Memory

October 7, 2014, 3:08 am
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Hello,

I would have one question related to user Flash Memory programming (UFM) on MAXV.

In the data sheet, there is written: "The targeted location in the UFM block that will be written must be in the
erased state (FFFFH) before initiating a WRITE operation" and "When the UFM sector is erased, it has 16-bit locations all filled with FFFF".

If I want to write a data at adress #10 of sector 0, this location #10 needs to be 0xFFFF to be able to write a new data. I checked this, it works.

Correct me now if I am wrong now: If I want to rewrite a new data at this same address #10, I need first to save all data's of sector 0, erase sector 0 with command 0x20 (all sector 0 will be then 0xFFFF) and then, rewrite all sector 0 data's, including the data that I wanted to write initially. Am I right?

Thank you in advance for your comments.

Fabe
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Simple pin assignments using text file

October 7, 2014, 4:04 am
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Hi,
I am just starting out with Quartus II Free 13.1 using an EP3C40U48417 device.
We use the device in the main to allow us to change peripheral to processor pin allocations.
Our processor has a pin multiplexing function.

I would like to automate the configuration of the FPGA using the processor's pin multiplexor settings.
This is a simple programming job if I can use a text file to map one FPGA pin to another e.g.

PIN_G10 to PIN_F5
PIN_A7 to PIN_E16

What format text file must I use? Where does that text file go in the project.
I found an example project's .qsf file which seemed to contain pin mapping details but the file did not update as I added new pins.
I am not sure how the project elements fit together.
A few key words would help me get started & read the correct sections.
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How to clear the Nios II console?

October 7, 2014, 4:33 am
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Hi,
I'm implementing a Nios II on a DE0-nano board. My C code is executed by Eclipse and a console is accessible to print things (with the printf instruction). I'd like to clear this console but I don't know how to do it.
Does someone know?
Thanks.
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Problem face while working with Alarm

October 7, 2014, 5:31 am
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Currently I am working on application where I am using Alarm to switch on the LED after 4sec.
But after calling the function alt_alarm_strt with a configured delay of 4sec, what I have observed is that, the LED is taking more than 4 secs to switch on. (~5 sec)

Genera info:
Quarts 64-Bit Version 13.1.0 Buld 162
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Nichestack driver for 10GbE

October 7, 2014, 6:11 am
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Hi,

I am looking for a driver to use the Altera Nichestack on the 10GbE MAC.
Has anybody done that job already?

regards
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Cyclone IV EP4CE15 FPGA JTAG programming issue

October 7, 2014, 7:17 am
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Hello,

I have USB Blaster Rev. C and I have ready made .Jic file only for my FPGA. (I have no other file except .Jic file)
My FPGA chip is on the main board and also have a JTAG connector on it.

FPGA is Cyclone IV type - EP4CE15F256

I downloaded Quartus Programmer and also I have USB blaster drive for windows 7 64 bits and also programmer detect it successful.

But when I try to programmed it, it showed programming failed error.

So my questions are,

Is there any setting to do specially for the Cyclone IV series device ?
Also Is there any way to program it by setting in software / Hardware manually or any other way ?

Please let me know about it if there any.
Help me in this issue for programming my device.
Please reply me about it with necessary details.

Regards

Thanks in advance

Jaymin D
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TRACE Debug on Cyclone V HPS - has anyone used DSTREAM

October 7, 2014, 7:53 am
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I am trying to use the TRACE Port peripheral on the HPS in a Cyclone V SE device. I cannot seem to get the TRACE signals coming out of the device properly to run the TRACE Capture using the DSTREAM 4GB Trace Buffer. I'm not sure the peripheral and pin MUX settings have been generated properly for my project because the data lines never seem to toggle.

I have been able to run the TRACE capture in DS-5 using DSTREAM over the JTAG interface. This works as expected. Unfortunately, I cannot say the same about the parallel TRACE peripheral interface.

Has anyone tried to use the DSTREAM TRACE peripheral interface? Was it successful or did you run into similar problems?

If you had success, what device did you target? (I am trying to connect to a 5CSEBA2U23C7SN device.)
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Can't configure Cyclone 2 via ipbus

October 7, 2014, 9:30 am
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Hi all,

I'm a complete rookie on FPGAs, so it is possible I'm doing something silly. I've been trying to load the example program onto our Cyclone 2 without any luck.

My procedure is to parse the Intel hex file provided by Altera and write each data byte to the configuration register one at a time. The nStatus and Configuration bits remain high during the process, but the FPGA never enters user mode. The only other clue I could find is that the CRC_ERROR bit is always high during the configuration. I never set the device up to use CRC, so I'm not sure if that is just being ignored or actually reporting an error. Could that be indicative of a hardware problem? Any advice is greatly appreciated as I've been hitting my head against this wall for a few days now.

Matthias
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Arria V: VOD values for LVDS i/o

October 7, 2014, 2:09 pm
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Hello,

I can see in the Arria V handbook that we can have 3 settings for LVDS TX I/O. 0, 1 and 2. I am wondering what these would correspond to on the board assuming 100ohm termination at the far end. Please note, that I am not asking for the xcvrs. Rather the LVDS i/os.

Anyone know where I can get this information? I cannot find it in the datasheet as well.

TIA.
Best regards,
Sanjay
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TCL Window to read compile parameters

October 7, 2014, 4:35 pm
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Is there a way to launch a window to read a few parameters when we hit the compile button in Quartus GUI? I have a pre_flow tcl script that is executed to create a revision for the compile. Now I need to provide some additional parameters to the build. I am hoping I can reuse the same pre_flow script to provide this feature. I am envisioning providing a pop-up where the engineer inputs the value hits return and then the compilation process continues. It doesn't have to be a pop-up as long as there is way for users to enter the data.

Want to prevent any excuses to forgetting to rev up the revision before a compile.

Thank you.
Best regards,
Sanjay
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Some blocks are not synthesized

October 7, 2014, 5:27 pm
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Pins Not Configurable (always high/low)

October 7, 2014, 10:45 pm
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Hi,

I'm working with Stratix IV GX FPGA Development Kit.

When I used HSMC port, there're some pins not configurable.

I can set these pins as output pins in Quartus II, but their output level never change.

For instance,
AW6 --> always HIGH
AW5 --> always HIGH
AV5 --> always HIGH
AW4 --> always LOW
AR5 --> always LOW
AT5 --> always LOW
(... and there're much more)

I've checked user manual but still got no idea.

Any help or comment are appreciated.

Thanks a lot.
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Metastability test inside FPGA

October 8, 2014, 12:59 am
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Hi all!

I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints.
I think it will be very representative if a part of design that doesn't meet timing, falls into a metastable state and after that a problem will be fixed adding constraints.

Can someone help me with any ideas, how to create a code which will mostly representative crashes if a metastable situation occurs (internal counter stops, dead state enters, etc)?
And how to visualize it better (signal tap, signal probe, iLEDs maybe).



Thanks in advance.
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Using VIP suite with Triple Speed Ethernet (TSE)

October 8, 2014, 5:27 am
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Hallo,

i am working on a small Project with the Triple Speed Ethernet and VIP suite (Video and Image processing Suite).


I need to send the data from the Testpattern Generator IP via Ethernet and show them in VLC Player.

Did anyone try to combine such two IPs ? I searched a lot to find any example in QSYS to start with and didnt find any.

Thanks a lot for any help !
Jalayan
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nios ii doesn't run hello world (or sometimes not correctly)

October 8, 2014, 5:40 am
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Hi Guys,

i have a problem with the niosii. I use a Altera Cyclone IV EP4CE22E22C8N on a selfmade board. The board now only contains a 60MHz Clock, the fpga and a sdram. The Reset and exception vectors are both in the sdram.
The Problem is that after a creation of a niosii based system in Qsys (in older quartus versions sopc-builder) and creating a hello world program in NiosII 13.1 Software Build Tool for Eclipse, the niosii doesn't run. Sometimes he run but doesn'T works correctly. Instread of writing Hello from NIOS II for 100 times and counting the number down, i get this:

llo from Nios II! 96
Hello from Nios II! 95
Hello from Nios II! 99
Hello froHello from Nios II! 99
HHello from Nios II! 99
HeHello from Nios II! 99
Hello froHello from Nios II! 99
.
.
.


:confused::confused:

But as i wrote abovde in the most times i don't get anything from the nios ii.
Do someone has an idea where the problem could be ?;):cool:
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Debugging Transceiver Links

October 8, 2014, 6:17 am
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Hi, I'm quartus II beginner.
I want to modify the number of channels, bit rate, and clock in an Altera design example <transceiver_toolkit_13_0sp1_qar/ sv_4ch_32b_6445mbps>.
so I added channels by creating more Avalon-ST Data Pattern Generator, checker, and other related IP Core and modified bit rate an clock and then generated modified v.file.
And then compiled the files.
However, channel manager in transceiver toolkit GUI shows still previous set-up.
In other words, there is no added channel and bit rate and clock is same with before.
I don't know how to update the transceiver links.
How can I solve this problem?

Thanks.
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Ideas for my thesis using DE1-SoC development board and DSP Builder tool.

October 8, 2014, 7:37 am
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Hi,

I am working in my master degree thesis using DE1-SoC development board. Now I am doing the user interface using a hard processor system (HPS ARM) with linux embedded to control a Terasic Multi-touch LCD module.
I need some ideas to do some ip core in fpga such as digital signal processing for audio or communications, or other things.

Thanks.
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Ideas for my thesis using DE1-SoC development board and DSP Builder tool.

October 8, 2014, 7:42 am
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Hi,


I am working in my master degree thesis using DE1-SoC development board. Now I am doing the user interface using a hard processor system (HPS ARM) with linux embedded to control a Terasic Multi-touch LCD module.
I need some ideas to do some ip core in fpga such as digital signal processing for audio or communications, or other things.


Thanks.
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