timing problem 1
hi everyone:
in my design, there is a pll to provide clk for outside sdram.
my generate clk in sdc file
create_generated_clock -name {SDRAM_CLK} -source [get_pins {inst2|altpll|sd1|pll7|clk[0]}] -master_clock {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0]}
create_generated_clock -name {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0]} -source [get_pins {inst2|altpll|sd1|pll7|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 288.000 -master_clock {EXT_CLK} [get_pins {inst2|altpll|sd1|pll7|clk[0]}]
create_generated_clock -name {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[1]} -source [get_pins {inst2|altpll|sd1|pll7|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {EXT_CLK} [get_pins {inst2|altpll|sd1|pll7|clk[1]}]
create_generated_clock -name {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[2]} -source [get_pins {inst2|altpll|sd1|pll7|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {EXT_CLK} [get_pins {inst2|altpll|sd1|pll7|clk[2]}]
in order to constraint the output delay i do the follows:
#************************************************* *************
# Set Maximum Delay
#************************************************* *************
set_max_delay -from [get_clocks {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0]}] -to [get_ports {sdram_clk0}] 3.000
#************************************************* *************
# Set Minimum Delay
#************************************************* *************
set_min_delay -from [get_clocks {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0]}] -to [get_ports {sdram_clk0}] 0.000
the from clk's name is strange because i use the derive_pll_clocks -use_tan_name.
then the timing analyzer shows error, Registers to outputs error:
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i am so confused :
1.my contraint is the max and min delay from the output of the dll to the fpga output pin, why there are Register to Outpus (setup) and Register to Outpus (hold) error?
2.according to my generate clk :
create_generated_clock -name {SDRAM_CLK} -source [get_pins {inst2|altpll|sd1|pll7|clk[0]}] -master_clock {myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0]}
so in the error report,the from clk :myqsys:inst2|myqsys_altpll:altpll|myqsys_altpll_a ltpll_99h2:sd1|wire_pll7_clk[0] and the to clk :SDRAM_CLK, i think the are one clk.