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Problem with the Evalboard Terasic DE0_Nano with the AlterA Cyclone EP4CE22F17C6N

October 10, 2014, 7:37 am
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Hi guys,

i have another problem with the Terasic Evalboard DE0_Nano with the AlterA Cyclone EP4CE22F17C6N. I start the Demonstration DE0_Nano_SOPC_DEMO. After succesful Generating of the qip files and successful compilation in Quartus, i have a problem when starting a simple Hello World project with the board. Igenerate BSP and build the project successful. When I launch the Nios II I don't get the output i want in the Nios Console. Sometimes no output, sometimes the correct output and sometimes some strange letters.
It seems to be that there is no connection problem, because of correct SysId in the Launch Configuration.
The reset and exception Vectors are on the sdram of the board.
Does anyone has an idea what the problem could be?

Could it be a mistake in the configuration Launcher in the Nios Embedded Design Suite ?
:confused:
Does anyone have an idea ?
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Installing Devices on Quartus II Web Edition (Free)

October 10, 2014, 10:54 am
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I downloaded the combined files and installed Quartus II (14.0.0.300 64-bit) on my PC. I can't open a project unless I install the devices. The install dialogue asks for the directory that "contains the Quartus II device files (.qdz)." I can't find this anywhere.

How can I install the devices?

Thank You
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Altera Monitor Program issue on Win7 Pro (64-bit) (fresh install)

October 10, 2014, 11:09 am
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My desktop (not the machine mentioned in the title) had been working fine with Quartus, but when my class go to the point where we were going to work with assembly, AMP is having some issues. After much frustration trying to solve it, I eventually used a machine at the university where Quartus and AMP were already installed to compile the assembly and step through as it ran. Now, we're on the second assignment using assembly, and I've taken the time to do a fresh install of Win7 on my laptop, assuming whatever issues I'm having on my desktop are unique to it (no one else in the class has had issues and the professor couldn't figure out why it was exhibiting the behavior it was). After installing Windows 7, I did the following:


  • Installed drivers for the video card, trackpad, etc.
  • Installed Google Chrome
  • Installed Quartus II Web Edition v13.0 SP1 (I know it's not current; its the version the professor has instructed us to use, and the one installed on all of the machines at the university)
  • Installed Altera Monitor Program (through the University Program installer)



Although I doubt it has any chance of affecting my issue, I will mention that two files failed to install during the University Program install on both my laptop and desktop; they were something_HAL.d and .o in some examples folder, which is why I highly doubt they have any bearing on the issue.

On my fresh install, I redid the assignment entirely on my laptop. The only things I did not redo from scratch were the verilog and assembly files since I had already looked over them for errors several times. I create the project in AMP, hit Finish, and it asks if I want to load it onto the board. I say yes, it says it loaded it successfully, then I get a message about how I'm using a time sensitive feature (although the time remaining says Unlimited) with only one button (Disconnect), which I click. I'm not sure in what way it "disconnects" whatever it is disconnecting, but I'm wondering if it might be related to the issue that I run into next. I hit the button in AMP to compile & load so that I can step through the instructions as it works. Part-way through, I get this error: http://www.altera.com/support/kdb/so...7162014_6.html (the only difference being the numbers on the first line for the USB connection).

I read what the above page says, look through various forum posts online of people receiving similar messages (trying out any solutions I can find), double-check all of my settings, and finally just redo the assignment again from scratch (going through Qsys, etc.) only to receive the same error. Wanting to make sure there isn't something wrong with my installation, I try last week's assignment, downloaded straight from where I submitted it (so I know the files are current and work) and receive the same error. I regenerate in Qsys, recompile in Quartus, etc. and nothing changes; my file that I know should work (it did on the machines at the university) exhibits the same behavior as my new assignment.

And this is the point I'm lost at. I've ran out of things to try. If you're curious about the specifics of the assignment, last week's was simply instantiating the Nios II processor a modified version of the simple counter program in the tutorial (file is Introduction_to_the_Altera_Qsys_Tool.pdf, at least as my instructor uploaded it; I doubt he bothered to change the name). This week's assignment is doing the same thing but simply running a different assembly program, which can be found in section 10 of Nios2_introduction.pdf (still short program that does a dot product). I'll attach the .v and .s files for the current assignment; they should be pretty much the same as detailed in the pdfs aside from white space and comments, but maybe there's some error causing all my troubles that I'm overlooking (although I doubt it since last week's assignment isn't working on the laptop either).

Any help at all is appreciated, and if there's any other information I can provide that would be helpful, please let me know.
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Transceiver placement issue

October 10, 2014, 2:57 pm
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Hi,
There is one block, four transceivers in an EP4CGX22 FPGA chip. If i need to use it to design two independent transceiver links, each one with 2 transceiver channel bonded, is it OK?
Thanks a lot.

Yaoting
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TimeQuest User Guide Question

October 10, 2014, 3:13 pm
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I have a question regarding the virtual clock assignment described in the TimeQuest User's Guide on the web. I am not sure I understand how the virtual clock created for the set_input_delay and set_output delay constraints is related to the actual clock driving the logic in the FPGA.

I have the following constraint for CLK_FPGA which clocks all logic in the device:
create_clock -name { CLK_FPGA } -period 13.333 { CLK_FPGA }

Then, according to the paper, I create a virtual clock for I/O timing:
create_clock -name { CLK_VIRTUAL } -period 13.333

Then I set the I/O constraints (whose logic used CLK_FPGA) and relate them to CLK_VIRTUAL:
set_input_delay -max 5.000 -clock { CLK_VIRTUAL } [get_ports { LAD }]
set_input_delay -min 1.000 -clock { CLK_VIRTUAL } [get_ports { LAD }]

set_output_delay -max 8.000 -clock { CLK_VIRTUAL } [get_ports { DOUT }]
set_output_delay -min 2.000 -clock { CLK_VIRTUAL } [get_ports { DOUT }]

How is CLK_VIRTUAL associated with CLK_FPGA? They only have identical periods in the create_clock constraints, does that make them related?
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Why do I see termination logic option errors when I turn on design partitions?

October 10, 2014, 3:22 pm
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Using QII 14.0. My design successfully compiles when I turn of design partitions. But when I turn on design partition I get following error -
Error (169172): Output pin "adc_sense[2]" specifies a Termination logic option setting of Differential, however, only Series termination is allowed for output pins.

This output is defined to be a tri-state in the top-level using verilog as -
assign adc_sense[2] = (adc_sense_en) ? adc_sense_wire[2] : 'bz;

Any ideas on how I can fix or work around this?

BTW, I have following constraint in the QSF -
set_instance_assignment -name OUTPUT_TERMINATION OFF -to adc_sense[2]

Thank you.
Best regards,
Sanjay
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SDC Constraints for Asynchronous Interfaces

October 10, 2014, 3:42 pm
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I am trying to constrain some asynchronous interfaces which my FPGA interfaces to. I have a single FPGA clock, CLK_FPGA (period = 20ns) which clocks all logic in the FPGA. One asynchronous interface is an MRAM, and it does not have to be constrained within one CLK_FPGA period. It can be very slow.

First I tried the following:
create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA}
set_max_delay 80 -from [get_ports { MRAM_RDY }] -to {CLK_FPGA}
set_min_delay 0 -from [get_ports { MRAM_RDY }] -to {CLK_FPGA}
set_max_delay 80 -from {CLK_FPGA} -to [get_ports { MRAM_CS_N }]
set_max_delay 80 -from {CLK_FPGA} -to [get_ports { MRAM_CS_N }]

This seemed to work on some interfaces, but not on others. I am not sure why?

Then I tried the following:
create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA}
create_clock -name {CLK_ASYNC} -period 80
set_input_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }]
set_input_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }]
set_output_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}]
set_output_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}]

Again, this seemed to work on some interfaces, but not on others. I am not sure why?

Then in the paper TimeQuest User Guide, it mentioned a different method by using a virtual clock that matches the main clock, and using mutiple path constraints to specify the relaxed timing. Before I re-write my entire SDC file, does this method make sense? They would look something like this:
create_clock -name {CLK_FPGA} -period 20 {CLK_FPGA}
create_clock -name {CLK_ASYNC} -period 20
set_input_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }]
set_input_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_RDY }]
set_output_delay -max 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}]
set_output_delay -min 0.000 -clock {CLK_ASYNC} [get_ports { MRAM_CS_N}]
set_multicycle_path 4 -setup -from [get_ports { MRAM_RDY }]
set_multicycle_path 4 -hold -from [get_ports { MRAM_RDY }]
set_multicycle_path 4 -setup -to [get_ports { MRAM_CS_N}]
set_multicycle_path 4 -hold -to [get_ports { MRAM_CS_N}]

Any help or clarification would be appreciated.
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Arrow SoCKit Linaro Desktop with ACDS 14.0 and Linux 3.13

October 10, 2014, 4:25 pm
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Hi, I thought I'd provide some tips on using Arrow SoCKit Linaro Linux Desktop on ACDS 14.0, as I got it working just recently. This assumes you already have this one installed successfully:
http://www.rocketboards.org/foswiki/...roLinuxDesktop

* Used Makefile provided in <ACDS 14.0>/embedded/examples/hardware/cv_soc_devkit_ghrd

* The preloader and uboot image built seem to work fine this time.
make preloader uboot;
cd software/preloader;
cat preloader-mkpimage.bin u-boot.img > boot-partition.img
dd if=boot-partition.img bs=512 of=<boot partition of microsdcard>

* Use script git_clone.sh in embedded/embeddedsw/socfpga/source to get socfpga-3.13 kernel.
make socfpga_defconfig
make -j4 uImage

* Tedious: the default uImage is now too big for the default 10Mb partition on the microsd card. Went through menuconfig and turned off a lot of stuff. Also turned on CONFIG_FB and CONFIG_FB_ALTERA_VIP. My kernel .config file is attached as config-3.13.txt. This should just squeeze onto the boot partition with the uncompressed soc_system.rbf file.

* USB didn't work initially: that's because the default example cv_soc_devkit_ghrd soc_system.dts doesn't match the kernel dts. I copied hps_0_usb0 and hps_0_usb1 from arch/arm/boot/dts/socfpga.dtsi to my soc_system.dts (built from sopc2dts). Don't forget usbphy0. I then had to compile the dts to dtb using Altera's 13.1 embedded/hotools/gnu/H-i686-pc-linux-gnu/bin/dtc which is no longer provided in 14.0.

Working HPS USB 3.13 DTS looks like this:

usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};


hps_0_usb1: usb@0xffb40000 {
compatible = "snps,dwc2";
reg = < 0xFFB40000 0x0000FFFF >;
interrupt-parent = < &hps_0_arm_gic_0 >;
interrupts = < 0 128 4 >;
clocks = < &usb_mp_clk >;
clock-names = "otg";
phys = <&usbphy0>;
phy-names = "usb2-phy";
enable-dynamic-fifo = <1>;
host-rx-fifo-size = <0xa00>;
host-perio-tx-fifo-size = <0xa00>;
host-nperio-tx-fifo-size = <0xa00>;
dma-desc-enable = <0>;
status = "okay";
}; //end usb@0xffb40000 (hps_0_usb1)

* The qsys file auto-upgraded to 14.0 without problems.

That got me booted up and running Linaro.
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CAS Latency on Cyclone V DDR2 Hard Memory Controller

October 10, 2014, 5:01 pm
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When running simulations using the Cyclone V DDR2 HMC UNIPHY simulation model I noticed something very strange.

If I set the CAS latency to 7, data is written correctly.

If I reconfigure HMC to CASL=5, the HMC will drive the DRAM with CASL=5 timing, however it will still set the SDRAM mode register to CASL=7. So the data latched into the SDRAM will be wrong.

Anybody have a clue?
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Πληρους Αθροιστή χρησιμοποιώντας έναν αποκωδι

October 11, 2014, 5:57 pm
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Θα ηθελα την βοηθεια σας σχετικα με την ένωση ενος Πλήρη αθροιστή του ενός bit χρησιμοποιώντας ένα αποκωδικοποιητή active low 3x8
(ολοκληρωμένο 74138) στο Quartus. Με ειδοδους Α,Β, Cin και εξοδους Cout και Sum
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CycloneIV adder behavior

October 12, 2014, 1:01 am
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Hi everyone,

I have a snippet of code that adds.
Code:
    logic bitCount[3:0];
    always_ff @ (negedge sck, posedge cs)
    begin
        if (cs)
            bitCount <= 4'b0000;
        else
        begin
            bitCount <= bitCount + 4'b0001;
        end
    end
This code returns the desired value by the next clock cycle. However, if I increase the bit width of bitCount above 4 bits, the sum does not return by the next clock cycle but the clock cycle afterwards. Can someone explain whys this is? Does this relate to how the add function is implemented?
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_tb has no architecture (error in modelsim(of altera)(14.0)), plz help

October 12, 2014, 4:04 am
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simple program and its testbench(copy from book of volnei a. pedroni 2 e)
----------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------
ENTITY mydesign_tb IS
END ENTITY;
--------------------------
ARCHITECTURE testbench OF mydesign_tb IS
---DUT declaration:------
COMPONENT mydesign IS
PORT (clk, rst, din: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END COMPONENT;
----signal declarations:-----
SIGNAL clk: STD_LOGIC := '0';
SIGNAL rst: STD_LOGIC := '1';
SIGNAL din: STD_LOGIC := '0';
BEGIN
---DUT instantiation:-----
dut: mydesign PORT MAP (clk, rst, din, dout);
----stimuli generation:-----
clk <= NOT clk AFTER 40ns;
rst <= '0' AFTER 80ns;
din <= '1' AFTER 160ns, '0' AFTER
240ns, '1' AFTER 32ns;
END ARCHITECTURE;
-----------------------
--------------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------
ENTITY mydesign IS
PORT (clk, rst, din: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END ENTITY;
----------------------
ARCHITECTURE mydesign OF mydesign IS
BEGIN
PROCESS (clk, rst)
VARIABLE q: STD_LOGIC_VECTOR(0 TO 3);
BEGIN
IF (rst='1') THEN
q := (OTHERS => '0');
ELSIF (clk'EVENT AND clk='1') THEN
q := din & q(0 TO 2);
END IF;
dout <= q(3);
END PROCESS;
END ARCHITECTURE;
------------------------------
but when I try to compile(both, error on tb-"unknown identifier dout") and simulate tb, error about no architecture of tb on my altera modelsim 14.0 on linux-ubuntu 14.04. plz help, eric
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Hard emi, Cyclone V SX, max speed

October 12, 2014, 10:38 am
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Hello. Who used Hard External Memory Interface on Cyclone V SX(Arrow SocKit board)? I can't get speed more than 140mbit/s via HPS2FPGA bridge with hard emi. With softcontroller I get a speed of around 240mbit for write. "Maximum frequency for MPFE is one-half of the interface frequency" (c) Functional Description Hard Memory Interface, but If i set speed over 50MHz, software write this errors. h2f bridge and Avalon MM burst length - 32bit
writes 0x10000 byte 1000 times:
SoftController
Memory Clock 300MHz:
root@socfpga:~# time ./memclock 0 0xc0000000 0x10000 1000

real 0m9.194s
user 0m9.180s
sys 0m0.000s

Memory Clock 400MHz:
root@socfpga:~# time ./memclock 0 0xc0000000 0x10000 1000

real 0m8.535s
user 0m8.520s
sys 0m0.000s

hard EMI
Memory Clock 300MHz,fifo 50MHz
root@socfpga:~# time ./memclock 0 0xc0000000 0x10000 1000

real 0m14.442s
user 0m14.430s
sys 0m0.000s

How I can configure it for max speed?
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Quartus Convert Partial Reconfiguration Programming Files

October 12, 2014, 10:43 am
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I am attempting to replicate the example provided on the Altera Wiki for partial reconfiguration. I compile using the provided .tcl file, and the only modification I make is to add a quartus.ini file with the line pgmio_write_pr_text_file=mif This is per the instruction in the compile script. After compilation, I notice that the generated .mif files are much larger (4511272 words vs. 336326 words) than the ones provided with the demo project. Since the ROM is 650000 words wide, these .mif are truncated by quartus.

I have tried using quartus version 12.1 and 13.1 and get the same result.
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Combining similar elements to single combo logic cell after Quartus compilation

October 12, 2014, 12:04 pm
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I have a question:
How I can disable combining similar elements to single combo logic cell after Quartus compilation process.

For example: I have a project like screenshot ("1-block_diagram.jpg" in attachment). In this project we have two "Exclusive OR gate" elements. Green rectangle highlighted is default Quartus II logic primitive symbol "Exclusive OR gate" element (from default library). Red highlighted rectangle is "Exclusive OR gate" element as combination AND, OR and NOT gate elements.

After compilation process we have next:

1) In RTL Viewer we can see that all is OK ("2-rtl_viewer.jpg" in attachment).

2) But as we can see in Technology Map Viewer - Post Fitting ("3_technology_map_viewer_post_fitting.jpg" in attachment) - Qartus combine this two "Exclusive OR gate" elements (green and red rectangle highlighted) as single logic combo cell.

And my question again:
How I can disable this combining similar gate elements to single combo logic cell after Quartus compilation process. I need this disabling for my task.

QAR archive file in attachment ("archive.qar").

Thanks in advance for any help.
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Hello World example produces many errors

October 12, 2014, 4:50 pm
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Hello, I am doing research using openCL at my university and we do not have a physical board.
My openCL compiler runs, by using the reference board s5_ref, but it produces many errors, so then I downloaded the files for Cyclone V SoC kit and tried it on c5soc

--log file is attached for c5soc run.

Both log files for s5_ref and c5soc look very similar.

I followed the instructions from the Altera OpenCL Getting Started.pdf for running the hello_world example.

Any help would be appreciated!
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SCFIFO wrreq and rdreq synchronisation

October 13, 2014, 3:57 am
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Hi folks,
just a quick question (hopefully),

In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO with my system synchronous clock, but make a write request to the fifo from an asynchronous source, does the megafunction sync it to my system clock for me, or am i expected to put in a two stage sync myself?

likewise for the rdreq signal?

The user guide seems to suggest that it is done for me, but I wasnt entirely sure!

many thanks for any advice.

deBoogle
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Enable L2 Cache

October 13, 2014, 6:31 am
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Hi!

Is there an simple(!) example on using the L2 Cache (using hwlib)?


My current test project places some code(some few KB) at 32MB offset (0x0200 0000), so i guess it ends up in DDR Ram.

All alt_cache_* functions are placed in on-chip-ram at 0xFFFF0000.

This is what i do:
- setup interrupt vector
- call alt_cache_system_enable
- assign one variable to another

This is what happens:
- code runs fine
- the variable assignment results in wierd behaviour. "step over source line" doesn't work anymore, i guess the cpu just goes wild.

Enabling the L1 Cache without L2 Cache works so far, but thats not even the half story. ;)

I guess i need to setup the MMU bevore calling alt_cache_system_enable.

So i tried the following code. One section that spans 64MB, starting from address 0:
Code:
ALT_MMU_MEM_REGION_t regions[1];

regions[0]= (ALT_MMU_MEM_REGION_t)
{
    .va        = 0x00000000,
    .pa        = 0x00000000,
    .size      = 64*1024*1024,
    .access    = ALT_MMU_AP_PRIV_ACCESS,
    .attributes = ALT_MMU_ATTR_WBA,
    .shareable  = ALT_MMU_TTB_S_NON_SHAREABLE,
    .execute    = ALT_MMU_TTB_XN_DISABLE,
    .security  = ALT_MMU_TTB_NS_SECURE
};

uint32_t * ttb1 = NULL;
status = alt_mmu_va_space_create(&ttb1, regions, 1, alt_pt_alloc, alt_pt_storage);
no luck there, cpu goes wild in alt_mmu_va_space_create.

any hints/code?
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Mysterious sopc_altera_pll directories in my home directory

October 13, 2014, 5:34 pm
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I have been noticing that empty directories are getting created in my home directory when I run ip-generate. The directories have names of the form sopc_altera_pll<secs><digits> where <secs> is the current time since Jan 1 1970 and <digits> are just random digits (could be sub-seconds times). This is with the Quartus 14.0 and running on Linux.

Has anyone else seen anything like this?
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Interfacing with Altera-MM Salve of UniPHY DDR2 controller

October 14, 2014, 1:02 am
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Hi to all....
This is my first post in this forum and my english is not quite good...


I have some problem with a UniPHY interface generated trought Megawizard (Quartus II 13.0 with a Stratix IV device) for the interface with a DDR2 memory.


As I read in the documentation and in this forum I have in the user side an Avalon-MM Slave interface so I used the Avalon specification chapter 3.


I have some doubts

  • respect the sincronizzatio of the avalon interface: The signal ( in particular the avl_ready = not(waitrequest)) changes on the clock edge so if I use a statement like @(posedge clk) I read the state only on the following clock edge cause two read request.




  • Wher i can find the properties of the generated Avalon-MM interface listed in the table 3-2 of the Avalon Specification?



First I must write data in the interface otherwise when I try to read the interface return "x" data.


When I use a write burst size of "1" and make a read request (also with burst size 1) the interface return to two valid data.
Figure 1-1


When I use a write burst size of "1" and make a read request with burst size =3 the interface return 3 valid data but the first two are egual.


Figure1-3






Otherwise when I use a write burst size different from 1 the following read request are ignored.
figure 21
figure 2-3


This is the question... More Important is to find the properties of the interface because I'm not sure on the addressing and data size of the Avalon-MM interface.


Thanks to all!

Edit: Sorry but I can't upload image. Return an invalide file. The image are a .png of size less then 100kb. Suggestion?
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