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DDR3L on cyclone V E (HMC)

October 14, 2014, 1:05 am
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Does the cyclone V (5CEFA4F23I7) support DDR3L in Hard Memory Controller ?
Handbook says: The SDRAM controller offers the following features: Low-voltage 1.35V DDR3L and 1.2V DDR3U support.
But it refers to HPS, but i want to use HMC with dedicated pins and I'm not 100% sure.
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sequential circuit power

October 14, 2014, 1:17 am
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I request you to let me know the following.
i have sequential circuit consuming p mW using PowerAnalyzer in Quartus II. I duplicate the sequential circuit. I find that power is now q mW where q is not equal to 2p. Let q = p+x. If i have n copies of the sequential circuit ( eg. inputs to array elements) can I conclude that the power of this circuit is
p+(n-1)x?
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jpeg image library code in verilog

October 14, 2014, 5:03 am
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I need jpeg image library code in verilog for read an image in the sram memory.
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MODELSIM error vsim-3807

October 14, 2014, 5:11 am
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Hi folks,

I have recently encountered a problem which I have not seen before, even though I am following the same design/synth/sim flow as I usually do. Basically, when I go to RTL simulate in MODELSIM i get the VSIM-3807 error, on closer inspection it says I have type mismatch in one of my VHDL files.

The VHDL file i have created has the following declarations:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

and I only use UNSIGNED and no STD_LOGIC_VECTORS although i do use STD_LOGIC.

I have various megafunctions as well as a BSF file created from my own vhdl file all connected in a BDF. i then create a vhdl file from this BDF and include in the project and set as top level entity (the BDF file is not included in the project). And then I compile.

When I examine the created vhd file against the errors shown in MODELSIM, i can see that the component port declarations used are STD_LOGIC_VECTOR even though in my original VHDL file they were defined as UNSIGNED.
The declarations at the top of the vhd file created from my BDF does not include the IEEE.NUMERIC_STD.ALL;

I don't understand why this type mismatch has occurred.

Can anyone give me some hints please

Many thanks in advance
deBoogle
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Baremetal appication(LED Blinking)

October 14, 2014, 5:12 am
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Hello,

Am working with Macnica Helio SoC kit. Am using Helio kit's Golden Hardware design in quartus. Can anyone help me with the following issues.
1) How to develop a Baremetal application blink the LED's?
2)How to create and Debugg the project in DS-5?

I want any related to documents/example projects/tutorials to solve above issues.


Thank you.
Madhu Mamidala.
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Refreshing older FPGA with Avalon OpenCores 10/100 Ethernet MAC

October 14, 2014, 8:17 am
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Hello! We are working on an FPGA with the older Avalon OpenCores 10/100 Ethernet MAC (v8.02) which was completed in ~2009 using Quartus 8.x and SOPC builder on a Cyclone III. We have ported the functionality to a new Cyclone IV now using Quartus 13.1 but without converting the SOPC builder component to QSYS.


There is an issue currently where after pinging for some period of time (approximately overnight) the Ethernet MAC stops sending the interrupt to the processor for received data packets (only). We can see the TX data going out, the TX interrupt occurs, and the receive data comes back (RXDV is active), however no RX interrupt occurs. Once the FPGA is in this mode, it stays there until it is reset and will never send another RX interrupt until then.


　
1) Has anyone experienced this?
2) Any thoughts on what may be causing it?

3) What would the impact to software be of using the TSE? Is there a Linux driver available?

3) Is it possible to port this from SOPC builder to a QSYS implementation? We would like to use a newer version of the core and see if that fixes it. 8.03 seems to be the newest "stable" version. Jakobjones created a beta version 9.1 sometime in 2010 but it doesn't appear to have ever been finalized based on the searches I've done.


Thanks a lot!
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Question about warning: "Port type is incompatible with connection (port 'clock')"

October 14, 2014, 10:13 am
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The warning was issued after simulating a module written by Verilog.

# Region: /.../.../.../u1/lpm_mult_component
# ** Warning: (vsim-3016) C:/.../.../.../multiplier.v(62): Port type is incompatible with connection (port 'clock').

The module has a clock input "clk" which is assigned directly to a multipier generated by the megafunction. The warning refers to the "clock" signal within the multiplier.

I don't understand why this warning was issued since the "clk" signal is defined as "input" and the "clock" signal within the multiplier is defined as "input" by the megafunction. Port type should be compatible.


Any suggestion please?
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Using QDRII with NIOS

October 14, 2014, 12:22 pm
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I want to use the QDRII SRAM on the Arria V GT dev board as memory for a NIOS processor. The QDR has separate Avalon MM ports for read and write, but I think they must be assigned the same address range to work as NIOS memory. But Qsys complains about address overlap. It seems Qsys doesn't understand a read-only or write-only Avalon slave, so it thinks they conflict. Qsys view is attached.

Attached Images
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Question regarding loading the SRAM with .ram files and additional .sof file

October 14, 2014, 1:10 pm
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Greetings,

In one of our course project, we are to design a small processor which requires instructions to be fetched from the SRAM memory. The procedure given is as follows:

1. We open the "DE2_115_ControlPanel.sof" with Quartus, and select the option to open a new programmer configuration. We then program this file onto our FPGA board.

2. We open "DE2_115_ControlPanel.exe" and load the .ram file, which contains our instruction into our FPGA board.

3. We open up a new programmer and select our processor.sof file and program it into our FPGA board.

Later we realized that this procedure is faulty as the second program to the board (step 3) will overwrite the .ram data (instructions) we have previously loaded onto the board.

We were able to find a solution to this problem: repeating step 2 multiple times, and the memory will not be corrupted somehow.

Still, I would like to ask some questions:
1. What is the "correct" way to do this? I believe there has got to be a more reasonable solution to this problem. For instance, can we specify the address of our second loading so that it does not corrupt the memory file?

2. I initially tried to fix this program by first converting the processor.sof file to a .pof file and load it onto the board. I believed this method would allow the program to stay in a different memory location. (I assume this because it has got to be some sort of non-volatile memory structure as opposed to SRAM, is it FLASH?) But then to load the .ram file I will have to load the "DE2_115_ControlPanel.sof". So how can I return to the processor code I have programmed? Is there some sort of soft-reset that preserves the SRAM data and returns me to the pof file?

3. This is more of a minor question but I think it's quite interesting: why did our solution worked? What is special about writing the SRAM with the same file at the same location multiple times?

Board we used:
DE2115 CYCLONE IV DEVICE : EP4CE115F297CN



Thanks in advance.
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Debugging with the Nios II 14.0 Software Build Tools

October 14, 2014, 1:51 pm
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I am unable to debug in the Nios II 14.0 Software Build Tools for Eclipse environment. Attempting to do so produces these messages:
'Launching ... configurtion' has encountered a problem.
Error starting gdbserver - see console for details.
There is no information in the console window. I am surprised that there is reliance on gdbserver, as my embedded project is not Linux-based.

I have set STDIN, STDOUT, and STDERR to the JTAG UART. A Terasic Blaster is the only connection between my PC and my Altera development board (i.e., no Ethernet). Are any of these facts interfering with debugging?

TIA for any help )
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SoC Dev Kit Quality of Experience Survey

October 14, 2014, 4:33 pm
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SoC Dev Kit Quality of Experience Survey

October 14, 2014, 4:36 pm
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Diagnose AOC: Internal Compiler Error

October 14, 2014, 9:04 pm
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Hi all,

I've been using the Altera OpenCL SDK for about a month now with no issues, but suddenly I have come across the dreaded "Error: Internal Compiler Error" prompt.
The last thing I would like to do is reinstall the SDK if there is a quick fix available, but I do not really know how I can diagnose the issue.

The kernels were compiling successfully uptil recently. I checked with kernels that successfully compiled in the past, and even with examples from Altera's site.
The .log file doesn't show anything out of the ordinary. "aocl daignose" returns "diagnostic_passed" on the device, but anyway I'm pretty sure it's an issue with the software.

Is there any way I can diagnose the issue without a reinstall of the SDK?

Regards,
Victor
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Problem with SOPC to QSys Migration

October 14, 2014, 10:37 pm
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Hello everyone! I'm extremely new with the Quartus Software, and I'm assisting a person with simple tasks. I was asked to investigate how to migrate SOPC to Qsys, which I did and eventhough I had never used the software before, it seemed pretty easy. I watched the video tutorial in Altera; however, I'm having a problem (it's probably a quick fix thing, but like I said before, I have never used neither Quartus nor Qsys). The video tutorial explains that in order to migrate SOPC Builder to Qsys, first and foremost i have to launch Qsys, click on File, then OPEN and select an existing sopc file. My problem is that whenever I Clic open, my computer only searches for .qsys files, and all of the other files including the .sopc that I cannot be chosen, because they are not displayed. I have the actual file in my computer, but whenever I click FILE and then OPEN on Qsys, the file won't show because my laptop only displays .qsys files and I CANNOT change this option, meaning that I cannot open the .sopc file. Like I said, I'm new to all of this, I hope that you guys can help me with this problem! Thank you in advance and have a nice day

I'll leave you the files that my boss (the person I'm assisting) wants to migrate, so that you can tell me if it is actually possible!
Attached Files
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Logical operation on vectors

October 15, 2014, 7:09 am
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I am trying to compile the following, simple kernel:

__kernel void foo() {
ulong2 l1 = (ulong2)(1UL, 1UL);
ulong2 l2 = (ulong2)(2UL, 2UL);
l1 && l2;
}

I'm using the following command to compile:

aoc -march=emulator -v <kernel_name> --board pcie385n_d5

, and I get the following error from the OpenCL parser:

invalid operands to binary expression ('ulong2' and 'ulong2')

I have noticed this with other logical operations, both unary and binary, and with other built-in scalar vector types.This is valid OpenCL according to the 1.0 specification. Looking at appendix A of the Altera OpenCL Programming Guide, there is no mention of restrictions placed on logical operations between scalar vectors. And this does compile correctly on other platforms (my CPU for example).

Is this an existing limitation that I missed or an oversight?

aoc --version:
Altera SDK for OpenCL, 64-Bit Offline Compiler
Version 14.0 Build 200
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Multiple (concatenated) DDR3 interface

October 15, 2014, 7:17 am
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Hello -

I am looking to design a DDR3 controller that interfaces to two 16-bit wide DDR3 memory devices as one 32-bit interface. On our board we plan to share address and control lines for the two devices, but each device would have their own DQ, DQS and DM signals.

I was looking at DDR3 Uniphy SDRAM controller's Ping Pong PHY architecture, but I do not think I want that, as it looks like it time multiplexes transactions between the two devices. We need 64-bits (2 * 2*16 bits) of data written on one memory clock, not across two clock cycles.

I attempted to build the DDR3 controller core using presets for our memory device, and just change the width from 16 to 32 bits. It looked like it changed the DQS and DM outputs from the core correctly, but then I realized that the calibration data from each 16-bit DDR3 device would be replicated twice on the aggregate 32-bit bus, and I doubt the one controller core would know how to handle that.

What I was thinking of doing was create a master and a slave core and encase them in a wrapper. The Master would share its PLL/DLL/OCT with the slave. The master core would drive both device's control, clock, clock enable signals, but each core would drive their own DQ, DQS, and DM signals.

Any reasons why that couldn't work?

Thanks.
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Stratix V QDR-II+ Controller PLL won't lock

October 15, 2014, 7:55 am
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We have a 5SGSED6N3F45C4N on a custom board connected to a Cypress CY7C2663KV18 QDR-II+ memory. We're providing a 100 MHz 1.5V DHSTL reference clock FPGA device pins BC8 and BD8 (the CLK11 pair) and trying to run the QDR-II+ memory interface at 200 MHz. Unfortunately, the PLL in the QDR controller won't lock. Using SignalTap, we observe the PLL lock indicator bouncing around, and using an oscilloscope on the output clock pins, we see the clock idle (railed high), operating at 200 MHz occasionally, and more often operating at 400 MHz.

What can cause the PLL in the Stratix V QDR-II+ controller to be unable to lock?
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Version control for the Quartus project

October 15, 2014, 11:03 am
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For project built in the Quartus, what files I need to commit to version control system? For HDL and sdc files are straightforward, how about files related IPs?

Meanwhile, what is the best approach for another designer to rebuild the committed project in their local copy?

Thanks in advance.
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modelsim vlog error syntax error, unexpected IDENTIFIER, expecting clocking

October 15, 2014, 11:48 am
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I cannot compile one of my verilog files in modelsim altera edition. I get this error using the global primitive.

# ** Error: (390): near "b2v_inst1": syntax error, unexpected IDENTIFIER, expecting clocking

global b2v_inst1( .in(LCLK1), .out(g_lclk1_c0));

Any ideas on how to fix ?

Thanks.
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DTB (Device Tree Blob Files) Step by Step Guide DE1-SoC ** HELP ! ** GPIO Q14.0

October 15, 2014, 12:39 pm
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I am developing a design on the DE1-SoC. I wanted to be able to drive some more GPIO from the HPS. The pins that were already GPIO in the GHRD work fine. After clicking the button in the HPS tab in QSYS, resolving the conflicts, I expected the new GPIO to be under HPS control. But no matter what I cannot drive them from the HPS.

I suspect (is this right?) that the GPIOs aren't working because I need a new device tree blob file. This is where things start getting difficult. The socfpga.dtb that is on the SD card image works. But it does not match the what is present in the GHRD, indeed when I swap the file on the card with the file in the GHRD, the ethernet port stopped working and there were some complaints on boot up about missing I²C.

What is really, really frustrating is that it appears there is no way I can build the *.dtb file from any of the files supplied with the GHRD.

There seems to be much conflicting information on this subject. For example it seems a clock.xml (Q13.1) file was needed but now isn't.
  • How do I create a suitable board.xml file?


Failing this it would helpful if I could replicate the process that built the socfpga.dtb that is already present on the SD card.

I hope some-one can help!
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