October 15, 2014, 12:49 pm
I have not written code to do this yet, but I thought I would describe my plan here in the hope that any experts present might give me a heads up on any possible problems.
I have a NIOS gathering data and placing it into the FPGA attached (16 bit bus) SDRAM. The HPS monitors and reads data from the SDRAM through the AXI bridge. Provided 32 bit words are written / read atomically I will have no problems. However I am somewhat worried about the SDRAM being attached by a 16 bit interface. I am not familiar with the details but expect that a 32-bit transfer from the NIOS to the SDRAM results in two (!) writes to the SDRAM. What if the HPS tries to read exactly in the middle of this write by the NIOS? Is it possible I could read half the old word and half of the new one? Or is the bus clever enough to make sure this does not happen?
Many thanks
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October 15, 2014, 2:29 pm
I am attempting to use sockit as an g_mass_storage device as a quick and dirty USB link.
I get the error "could not insert 'g_mass_storage': no such device" when I run modprobe.
I am creating the backing file with the following command:
dd if=/dev/null of=./disk-file.img bs=1M seek=1024 count=0
And attempting to load the the driver with the following command:
modprobe g-mass-storage file=./disk-file.img
I have looked at the device tree and the boot messages, it definitely looks like the Arm is aware of the OTG controller.
Thanks in advance,
Adam
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October 15, 2014, 2:31 pm
Hi everybody,
this is my first post .... so bear with me.
I am having some compilation issues in Quartus. I tried googling and found no answers. I tried posing a service request but i cant.
I am using 5CEBA2F17C6 cyclone VE. During my compilation i get this errors
Error (129001): Input port DINFIFORX on atom "lvds_control:lvds_init|lvds_sync:lvds_sync_init_T OP|lvds_deser_cy5:lvds_deser_inst1|altlvds_rx:ALTL VDS_RX_component|lvds_deser_cy5_lvds_rx1:auto_gene rated|sd1", which is a cyclonev_ir_fifo_userdes primitive, is not legally connected and/or configured Info (129003): Input port DINFIFORX[0] is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
Error (129001): Input port DINFIFORX on atom "lvds_control:lvds_init|lvds_sync:lvds_sync_init_B OTTOM|lvds_deser_cy5:lvds_deser_inst1|altlvds_rx:A LTLVDS_RX_component|lvds_deser_cy5_lvds_rx1:auto_g enerated|sd5", which is a cyclonev_ir_fifo_userdes primitive, is not legally connected and/or configured
Info (129003): Input port DINFIFORX[0] is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
can some one tell me what this is and how to fix it.
Thank you
Regards
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October 15, 2014, 2:47 pm
I have a logic design for a CPLD where a clock goes out on a device pin, and comes back in on another device pin with a fixed delay (say, 10 ns).
How can I best describe the incoming clock to TimeQuest, without losing the relationship to the outgoing clock ? I guess a virtual clock is out of the question, because it loses exactly that relationship. So should it be defined as a generic clock (which, by default, will relate it to its source, although I'm not entirely sure what that means in practice) ? Or as a generated clock (incoming = outgoing + 10 ns delay) ? Or is it impossible to keep the relationship available to the analysis ?
Any (informed) hints appreciated.
John Kortink
Windfall Engineering
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October 15, 2014, 8:59 pm
I am looking for a NIOS design that I can program on my Altera DE2-115 board (using Quartus II V14.0) on which I then run the "count binary" template that is part of the NIOS-Eclipse IDE. I am currently using a NIOS design that is part of one of the demo projects that come with the DE2-115 board (the USB device project), and with this NIOS design, I can see the counter counting on stout (via JTAGUART), but not on the board LEDs, 7-segment displays, or LCD display.
Thank you for your help,
Solaris
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October 15, 2014, 11:10 pm
I am using a DDR2 altmemphy controller IP for
Cyclone III FPGA EP3C120F780C7
DDR2 IC: MT47H32M8BP-3X1 for read/write application using nios-ii processor.
QSYS Connections are as shown in the ddr2_qsys.xps file below.
Included files.
1.ddr2_altmemphy.v top level file.
2.ddr2_altmemphy.qsf
3.ddr_altmemphy.out.sdc
4.altpll1.v
5.altpll1.qip
6.alt_ddr2.qsys
50MHz input clock
100MHz DDR2 altmemphy IP clock=PLL Reference Clock
Memory Clock Frequency: 150 MHz
Clarifications:
1. Is the Qsys system interconnection correct?
2.I have set DDR2 memory as both instruction and data memory, so when the processors compiles and executes the sample nios-ii application from bsp hello_world program it should display "Hello from Nios" in the nios-II console, but i am getting failed to download the elf error, what might be the reason?
3. How to write to the memory from the processor side, what is the command syntax? and what is the command syntax to read from the DDR2 memory?
4. What is the command from the processor side to control bank select ?
Regards,
Sriram
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October 16, 2014, 1:27 am
Hi, I prepare design with NiosII and SPI bus with 4 slaves. All slaves have different SPI standard (I mean clock polarity and clock phase to data). Is there a possibility to change SPI setup by the software? Is there some recommendation how to chnage clock signal in FPGA (between Nios and IO pin?). Or i need 4 SPI interfaces in Nios design and then connect bus together (I hope, you understand me.)?
Thanks,
Milan
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October 16, 2014, 1:51 am
Hi everyone!
I want to shift a number 24 bit to the right (cut off), and extract the remaining 8 bit. How to do it in VHDL?
a = b >>24 & 0xff;
So far I tried to work with srl, shift_right(), '&' and 'and' operators - actually nothing worked out. Running everything within a procedure, I have the following declarations
Code:
(...)
variable temp: integer range 0 to 65535;
variable d3: integer range 0 to 15;
(...)
-- and currently apply it the following way
d3 := to_integer(shift_right(unsigned(temp), 24)) and "11111111";
first I left away any "and" construction: d3 := to_integer(shift_right(unsigned(temp), 24));
Errors I obtain:Error: VHDL Use Clause error at increment_display.vhd(61): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible
...so I removed "unsigned()"
Error: VHDL error at increment_display.vhd(61): can't determine type of object at or near identifier "shift_right" -- found 0 possible types
...so I removed to_integer(), actually everything was already devined as integer, no?
Error: VHDL Qualified Expression error at increment_display.vhd(61): SHIFT_RIGHT type specified in Qualified Expression must match integer type that is implied for expression by context
...hum...
Actually, I could not find much or any example snippets on shifting and extracting, is there a totally different way of doing this in VHDL?
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October 16, 2014, 5:36 am
I am currently trying to implement a 32-bit wide DDR2 interface using 2x MT47H128M16RT-25E:C and a EP3C40F484Cx Cyclone III. When it comes to pin assignments for the data mask pins, I am a bit confused. Application note
AN-445 p. 9 states that DM pins on the memory device should be connected to DQ pins on the FPGA, while the
pin information for my device has both DQ and DM pins. Is it really the case that the DM pins on my FPGA should not be used?
Any shared thoughts or experiences on this would be highly appreciated!
Thomas
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October 16, 2014, 7:52 am
Hi all !
I am searching for a RTP library to work with th UCOS.
I searched the foroum und didnt find any clue how to get it work !
can someone please give me a hint how to implement RTP on UCOS ??
Thanks !!!
JALAYAN
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October 16, 2014, 10:25 am
Hi,
I just design a Basic X4 bonded transceiver by using ALTGX MegaWizard. I also wrap it with a transceiver reset module designed based on Spec requirement as well as an altgx_reconfig.v module included.
Well, next step is to write a simple test bench to generate parallel interface transmitting data. I connect the serial transmitting port to receiving port. In simulation wave form window i can see everything is going well except the data at parallel receiving output is always "9c9c9c9c9c9c9c9c", control signal byte is "11111111", never changed. Why? Any one can help?
Very appreciated!
Yaoting
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October 16, 2014, 1:04 pm
Hi everyone, I want know if there is a way to program an Altera CPLD using a linux command. Actually I want a command/program what you put only the .pof file and the program configure the device. I don't want the development environment, only the programming tool once I have the .pof files already, and I need to install this on a computer with few space on disk. Does someone know something about that?
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October 16, 2014, 1:38 pm
I was curious if there were a list of functions, in Nios ii using C, that convert decimal values to hex, binary etc... I am use to programming in Matlab so I am use to the quick and easy hex2dec converter. Thanks.
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October 16, 2014, 2:35 pm
We're having a really hard time getting SignalTap to work properly. We often get an "Invalid JTAG configuration" message and a "Compile the design before continuing" error for no apparent reason, when the design is completely up to date and has just been compiled. Even when it says "Invalid JTAG configuration", SignalTap will program the device just fine. In both cases, it will not allow us to observe the logic in the STP file.
There's very little information about what these two messages really mean. What could be causing these problems?
Thanks,
Danny
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October 16, 2014, 2:52 pm
As a bit of background, here is what I am trying to do.
I have a fairly simple synthesizer design hosted on an EP4CE15E22C7N (EQFP), which is driving an AD9744 parallel load DAC. The design is supposed to operate at 100MHz. Architecturally, the DAC and FPGA share a common clock, which is split and fed to both devices. The board designer serpentined the clock traces until they are almost identical - down to literally a couple of mils delta. He was thinking that it would be possible to drive the data from the FPGA to the DAC as if they were fully synchronous. I'm not clear if that was a good idea or not, but at least on the scope, they are right on top of each other.
I have tried to constrain the I/O to the DAC using the SDC file with a set_output_delay command. I did assume the board clock skew was close enough to ignore, calculated an estimate of the trace skew at ~600ps (these are surface traces on FR4, and are about 300-340 mils in length). Tsu on the DAC is 2ns, Th is 1.5ns. In theory, I should have plenty of time to get between the two parts.
set_output_delay -add_delay -clock [get_clocks {Master_Oscillator}] -max 2.600 [get_ports {DAC_Data[*]}]
set_output_delay -add_delay -clock [get_clocks {Master_Oscillator}] -min -0.900 [get_ports {DAC_Data[*]}]
When I checked, the failing pins are always the same 4 out of the 14. On closer inspection, they have an alternate Vref function, which I'm assuming is contributing to the larger data delay.
Two questions:
1) did I calculate the set_output_delay command correctly, and
2) Is there anything short of using a slower sample clock I can do to fix this if so?
I am not off by much:
-0.382 Composite_Out_q[9] DAC_Data[9] Master_Oscillator Master_Oscillator 10.000 -2.462 5.300
-0.373 Composite_Out_q[3] DAC_Data[3] Master_Oscillator Master_Oscillator 10.000 -2.453 5.300
-0.369 Composite_Out_q[13] DAC_Data[13] Master_Oscillator Master_Oscillator 10.000 -2.449 5.300
-0.356 Composite_Out_q[2] DAC_Data[2] Master_Oscillator Master_Oscillator 10.000 -2.436 5.300
vs
1.614 Composite_Out_q[8] DAC_Data[8] Master_Oscillator Master_Oscillator 10.000 -2.462 3.304
1.614 Composite_Out_q[7] DAC_Data[7] Master_Oscillator Master_Oscillator 10.000 -2.462 3.304
Thanks!
-Seth
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October 16, 2014, 7:26 pm
I am usign Quartus II to program an FPGA Cyclone 3. I am including the Nios Processor in my design.
I had it working initially satisfactorily. However, I made a few additions and modifications and for some reason the pins that I programmed as outputs are not responding. For example, I have an Avalon port on the nios called PING. This port is connected to an output ping. I have acecss to that pin in my hardware. When my software toggles the port, I cannot see the change in the pin. The port PING is not the only one that is not responding, there are two more, all of them are avalon PIO ports.
As I said everything was working before. I do not know if I corrupted something in the settings or exceeded some design thresholds.
I have checked and rechecked my sopc assignments. I have also regenerated the sopc, created new projects and BSPs to make sure all my system is upto date but I still have the problem.
I am using Eclipse to develop and test my software. In the debuggin process I have even tried to control the ports that are not recsponding via me memory window. I can control the ones that are ok, but not the PING port and the others.
At this time I am stripping down my design to a bare minimum to see if I can get to a point in which the remaining parts of the system behave properly. The problem is that each compilation takes 40 minutes... it is a pain.
Any suggestions?
Thanks
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October 16, 2014, 8:01 pm
Quartus II Programmer and Tools 14.0 for Linux (QuartusProgrammerSetup-14.0.0.200-linux.run in
http://dl.altera.com/?edition=subscr...platform=linux -> Additional Software -> Stand-Alone Software) fails in the installation of System Console with the following error message at the end of the installation process.
Quote:
/bin/sh: <install dir>/qprogrammer/sopc_builder/bin/system-console: No such file or directory
Surely, there is no qprogrammer/sopc_builder/bin/system-console file installed.
The installer places only qprogrammer/sopc_builder/model/* and qprogrammer/sopc_builder/system_console_macros/*.
It was confirmed that Quartus II Programmer and Tools 14.0 for Windows installs system-console.exe.
Any workaround in Linux?
OS: CentOS 6.5 x86_64
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October 16, 2014, 11:01 pm
Dear:
Now I want to use rapidio 1x to communicate with TMS320C6455, The FPGA is stratix V.
I don't want to use Qsys, so i use Avalon-ST Pass-Through Interface to instead it. is it right?
From the RapidIO MegaCore Function, Table 523 show that gen_rx_data and gen_tx_data is 64bit or 32bit depend on the lane mode.In my design, i use 1x mode so the gen_rx_data and gen_tx_datashould be 32bit, but i can't find the definition of 32bit gen_rx_data and gen_tx_data, there is only definition of 64bit gen_rx_data and gen_tx_datafrom Table 418 and Table 419. Who can tell me the definition of 32bit gen_rx_data and gen_tx_data?
Sorry, my english is not good, Thank you!
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October 17, 2014, 12:38 am
Hi Dears,
I design pice project according user guide, when i set parameters of pcie as UG i will get a error as below:
"Error: pcie_hard_ip_0.pcie_internal_hip: Stratix IV GX and Arria II GZ do not support a non-maximum RX buffer credit allocation"
So i can only change the setting to "Maximum" as attached file shows.
Could this be only a DOC debug?!
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October 17, 2014, 1:35 am
Hi,
I have a part of a big project and want to see graphical view of the netlist. For this purpose I'm going to do "Analysis & Elaboration" and then use "RTL Viewer" to analyse netlist.
But as I said I have only part of this project. And during "Analysis & Elaboration" I get 1.3k errors similar to this:
12006 Node instance "yyy" instantiates undefined entity "xxx"
This entities are not important for me. Only nets are interesting.
Are there any settings in Quartus that allow to replace these entities with black boxes and ignore them?
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