October 27, 2014, 5:51 pm
When I go to debug my assembly application to write it to my DE2 board (using confirmed proper .sopcinfo and .sof files), there is no "Nios II Hardware" debug configuration. I attached a screenshot to show what I'm talking about.
So, has anyone else run into this problem and know how to fix it?
Thanks!
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October 27, 2014, 6:28 pm
Hi all,
I am developing my project with Altera's Software. I am using it to upgrade POF file, ELF file for the development kit.
I have a C# .NET application to communicate with the development kit. :shock: I have a idea "Using my application to upgrade".
However, using COMMAND LINE, i have to install Altera's Software. It's wrong for me.:cry:
I don't know how to do that:confused:. Can you kindly share me about your help?:mellow:
thanks in advance.
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October 27, 2014, 11:29 pm
hai,
myself pooja and my project is about to watch movie on tv using nios2 embedded evaluatiom kit with ethernet connection..i had downloaded demonstrations like MTDB_VGA_TV and MTDB_LCD_TV.Above demonstrations uses dvd player as source but i have to play movie which is to be stored on sd card else playing through ethernet..how can i modify those demonstrations for my project..if anyone knows please mail me.......
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October 28, 2014, 2:23 am
Hi,
I am testing a custom cpu on SoC Devkit, since I don't need the presence of ARM HPS, I just
program directly the .sof file into the FPGA, and running in with the sdcard removed (I have another
project inside sdcard which is running GSRD on that sdcard).
Currently, I am testing a custom uart module and trying to print some letters from cpu through uart.
The tx pin is assigned to one of HSMC pinout (PIN G13), I use GPIO breakout board provided in the box,
In my other project, the gpio can output signal without problem, however, although I can see the signal
is outputting from tx on SignalTap, I can't observe any change on GPIO pin on my oscilloscope..
Is there any special configuration needed to run the Cyclone V FPGA without the HPS??
Thanks.
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October 28, 2014, 4:55 am
Hi,
I am trying to generate an EPCS64 pof file with sof and two hex files. One hex is my nios code (relative addressing). The second hex (absolute addressing with 0x7F0000 offset) is a tiny 64 char text string that I want to appear at the start of the last block of the epcs when programmed (this is an indicator that I can use for application specific flash status read).
If I generate the pof from just the sof and nios hex the generated file is exactly 8192 k bytes as expected. The individual sof and hex are only half the size of epcs64 so I guess the extra bytes generated are padding?.
However then if I add the tiny indicator hex (generated with 0x7F0000 offset) I get a device full "exceeds memory capacity" error from "Convert Programming File" Utility,
Anyone know how I can add this second hex file to the pof without exceeding the memory?
Or perhaps another method to insert the indicator string at specified epcs address?
Thanks,
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October 28, 2014, 5:08 am
Do all types of RAM allow the use of In-System Memory Editor?
I a trying to debug a Dual-port RAM , generated by the Megawizard. When I get to the "Mem Int" tab, I am looking for "Allow In-System Memory Content Editor to capture & update content independently of the system clock".
I see it for RAM:1 PORT, but not for RAM :2 port - anyone know why?
The "In-System Modification of Memory and Constants" chapter(QII53012) says use altsyncram, (which can be configured as Dual-port), but that is not an option available via the Megawizard in QII 11 sp1. (Device family Cyclone-II).
Thanks.
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October 28, 2014, 5:12 am
Hi,
I try to use ModelSim-Altera Start Edition from shell on 64bit Debian/Linux. When I double click on a signal of my project, loaded under "work", it crashes with the following message:
Code:
$ export PATH=${PATH}:/opt/altera/13.1/modelsim_ase/linuxaloem/
#...
# setting up project
$ vsim
Reading /opt/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl
** Fatal: Trouble with Simulation Kernel.
I already tried opeining Modelsim from Quartus II, there it seems to work. Any idea why it crashes?
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October 28, 2014, 7:53 am
Hi,
I am currently using quartus 14, though I had the same problem with earlier versions.
Basically if I do a a part of full compile - e.g. analysis & synthesis, fitting, etc., and then save and quit quartus, next time I open the project quartus doesn't remember that I compiled it, which means I have to run the process over again which for such a large project (based around a Stratix V), it wastes 40 minutes every morning.
Is there a setting I am missing to get quartus to remember it is compiled? or to force quartus into remembering?
I am using incremental compilation, but it still has to spend a long time analysing the source files and then fitting despite the fact none of the partitions need synthesising.
Regards,
Tom.
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October 28, 2014, 11:44 am
Hi,
For extraxting data from a 576Mbps serial datastream (subLVDS) with a DDR clock of 288MHz I would like to use the transceiver inputs of the Cyclone V.
Can I do this easily? Can I use the transceiver input as a diff. IO?
Thanks.
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October 28, 2014, 12:46 pm
Hi,
I'm using a MAX V CPLD (5M240ZM68C5), and sending a clock signal into a special function clock pin (CLK1, Pin E1). This signal is being used to: A) driving internal logic, and B) ideally, routed back out for external circuitry to use. I am, however, unable to have this clock signal appear externally on an output pin. Is there a reason? Is there a flag I can set that makes this possible?
Thanks in advance,
Shiva
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October 28, 2014, 4:37 pm
Hi,
This might be more of a general Ethernet question, but can someone quickly comment on how the PCS detects a link? I am starting with a design that features two 1000Base-X SFP modules to do a point to point connection without the MAC (so you could say it's on layer 1).
Am I supposed to send some data first? Or does the PCS periodically send some idle patterns / negotiation patterns to do that for me? Will I have to periodically send data to allow for stable clock recovery?
Please point me in the right direction :)
Cheers, Peter
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October 29, 2014, 2:56 am
Hi, simulating my code I have this problem:
# ** Error: Waveform.vwf.vt(59): near ",": syntax error, unexpected ','
# ** Error: c:/altera/14.0/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./decoder.do line 4
Error.
In some codes I use (as simple shift registers, sipo, piso) i had similar problems. In others no!
I specify that the codes compilation are always ok.
The code I use is in this case:
--decoder 4 in 16 output
library IEEE;
use ieee.std_logic_1164.all;
entity decoder is
port (
in_sel : in std_logic_vector (3 downto 0);
output : out std_logic_vector (7 downto 0)
);
end decoder;
architecture decoder_arc of decoder is
begin
A: process (in_sel)
begin
case in_sel is
when "0000" => output <= "00000001";
when "0001" => output <= "00000001";
when "0010" => output <= "00000010";
when "0011" => output <= "00000010";
when "0100" => output <= "00000100";
when "0101" => output <= "00000100";
when "0110" => output <= "00001000";
when "0111" => output <= "00001000";
when "1000" => output <= "00010000";
when "1001" => output <= "00010000";
when "1010" => output <= "00100000";
when "1011" => output <= "00100000";
when "1100" => output <= "01000000";
when "1101" => output <= "01000000";
when "1110" => output <= "10000000";
when "1111" => output <= "10000000";
end case;
end process A;
end architecture;
I attach the project.
Thanks for your attention!
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October 29, 2014, 3:29 am
Dear Moderator / Administrator,
We intend to refer to a thread from 2011 in a legal matter and would like to know whether the date and time shown in the header of a post concurs with the date and time it was actually posted by a member or whether this shows when it appeared after being released by staff.
Thanks for your reply!
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October 29, 2014, 5:12 am
Does anyone have instructions for building the fpga image for the nios example for the cyclone 3 starter board.
I can build the 'my first fpga' image (not tried to download it).
qsys has converted the sopc file, but I can't generate the fpga image - I think loads of files are missing, starting with sys_pll.v.
The altera doc assumes you are going to run a pre-built image.
I was hoping to use it to write/test some custom instructions.
Using a small dev board will give much faster complatioon times that using one of our own boards.
FWIW I'm hoping to run on linux (rather than windows), the tools (13.1.1) seem to be running fine - apart from the qsys window
not being movable from the top left corner!
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October 29, 2014, 6:13 am
I'm pretty sure I bit off more than I can chew, but I'm not willing to give up yet.
The class is really about compiler optimization. You pick up the IR spit out by LLVM and optimize it and hand it off to whatever backend you're using and then test to see if you made it better or worse -- pretty simple really. For whatever reason, I wanted to try to optimize for space and parallelizm in FPGA, so I picked a board at random (BeMicro CV) and ordered one and then started trying to figure out Quartus, Qsys, Nios II ... I'm having trouble figuring out what any of these tools really are, though I've had some success getting LEDs to blink and pins to spit out serial and so forth.
I'm under the impression Nios II is a library/layout/program that runs on the fpga. Do I have this much right? And I'm further under the impression that the BeMicro CV can run this (mainly because of this:
https://github.com/tommythorn/BeMicr...ster/nios_ddr3). Is this right?
I'm wondering if I can use clang (or a similar llvm compiler, of which there seem to be a few choices) to compile IR, *do my class project here*, then compile the IR to fpga using quartus/eds/etc and monitor the serials for program outputs on the BeMicro CV. Is this possible? Maybe use one of the various llvm2verilog compilers I'm finding? There's so much documentation on this site, I vacillate about whether I need 64 gigs of ram and a $5000 dev kit with a stratix pcie board or if I can do something really trivial on my little $50 board. It seems to me I can get something to work, but if I need to give up, it's better to know that this week rather than next week as a semester is only just so long.
(I'm not afraid to read docs, I'm just not sure where to dig in.)
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October 29, 2014, 8:25 am
I want create a license for
Quartus II Web Edition but I got: Sorry. There were errors encountered during the license generation. Please click
here to re-submit your request.
Please help me, I realy need it right now.
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October 29, 2014, 8:47 am
Hi,
I've been working on a fairly complex design which has several external devices (two ADCs, a DAC, and four voltage pulsers) which each have have clock and data lines that need constraining to check that they will meet the required setup/hold specs.
What gets a bit complex is that each IC will have its clock sourced from the FPGA to avoid the need for external LVDS clock buffers, but each clock within a group must remain as closely aligned as possible (no more than around 200ps out - ballpark figure), so for example the four pulser clocks must be aligned to each other, the two ADC clocks must be aligned.
With the ADCs the clock that is fed out is a sample clock which goes in to the ADC and then is returned shifted by anywhere between 10.3ns and 12ns internally after which it comes out as an LVDS frame clock. This frame clock feeds back into the FPGA to deserialise LVDS two groups of 8 data channels which may also need constraining.
The two frame clocks are shifted by 165 degrees during the deserialisation resulting in a parallel clock. Data is simply clocked back onto the original sample clock source to return it to the the sample clock domain so that the data from both ADCs is synchronised.
I've attached a drawing of an overview of the system.
I was wondering if someone could guide me through constraining this design as although I have read through several documents on timequest and source-synchronous signals, its not really sinking in and so I don't really know what I am doing (and the effect the commands are having) to put it bluntly.
Any advice would be greatly appreciated.
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October 29, 2014, 8:49 am
Hi,
I would like to generate a crystal resonator clock in an FPGA, i.e. connect an external quartz resonator (and not oscillator) to an internal digital NOT (inverter) gate of an fpga, similarly to a microprocessor (Pierce-Gate crystal oscillator circuit).
Can it be implemented?
Thank you and kind regards.
Varouj
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October 29, 2014, 9:02 am
Hi,
Another beginners understanding problem..
In the following module I try to provide some input at "writedata", and "write" signal, and expect some incremented output on "readdata" and a "done" signal set. When I test the code with ModelSim, I see the assignment to readdata actually never happens. Actually the line of the assignment to readdata is not even breakpoint-able in ModelSim, it tells "no executible line". Why is that? How may I achieve an incremented assignment here, and what am I doing wrong?
Code:
...
reg [7:0] algo_out;
initial algo_out = 8'b0;
...
EDIT: I posted the wrong code snippet, pls have a look into my other post, below! Sorry about all the mess!
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October 29, 2014, 9:23 am
Hi, I've started yesterday with ModelSim. Since I'm learning it my own and don't know who to ask, I'm posting this probably stupid question to you (sorry).
I saw when I have input signals to my verilog module, in ModelSim I'll have to explicitely set them, even to 0, alternatively they stay undefined. I read that I always should set not just the clock, but also a reset signal happening after certain period of time in the beginning. Now, I need a "start" impulse happening, and I noticed simply setting "start" to high after a certain time, leaves it high forever. So, I'm currently setting it then later to low. I'm trying to model here a 50 MHz clock.
Currently I'm doing it e.g. like this in transcript:
Code:
force -deposit /reset 0 0, 1 50 ns, 0 100 ns
force -deposit clk 1 0, 0 {10 ns} -repeat 20 ns
force /start 0 0, 1 100 ns, 0 200 ns
The module declaration looks as follows..
Code:
module algo(
input clk,
input start,
input reset,
output reg [3:0] leds,
input write,
input [7:0] writedata,
output reg [7:0] readdata,
output done
);
Questions:
Am I doing this actually correctly?
In my Verilog design should I also try to set signals to low when they're handled, e.g. the "start"?
When giving e.g. the start impulse, for how long actually should I leave it high in ModelSim?
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