October 29, 2014, 9:43 am
Hi,
I just installed Quartus II 14.0.0.200 alongside Quartus II 13.something so I can test it before deploying it. But in my present designs, I can't update block symbols (of compnents generated in QSys) anymore?
Is it Altera, or is it just me?
Cheers, Peter
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October 29, 2014, 2:16 pm
Looks like using a Dashboard in System Console is a great way to debug hardware. I am able to write TCL commands to create the dashboard, show the dashboard, add buttons etc. But I have difficulty figuring out how to organize the code (into functions instead of just lines of TCL code).
I am starting out simple, just two buttons and an LED. Start Motor, Stop Motor and Motor_Running LED
This is what I have as a starting point:
################################################## ################################
# Motor Control
set dash_path [add_service dashboard my_dash "My Dash" "Tools/My Dash"]
# Set dashboard visible
dashboard_set_property $dash_path self visible true
dashboard_add $dash_path G1 group self
dashboard_set_property $dash_path G1 title "Motor Control"
# Add Button for Start Motor, Stop Motor
dashboard_add $dash_path BtnStart button G1
dashboard_set_property $dash_path BtnStart text "Start Motor"
dashboard_set_property $dash_path BtnStart onClick
[list StartMotor "Running"]
dashboard_add $dash_path BtnStop button G1
dashboard_set_property $dash_path BtnStop text "Stop Motor"
dashboard_set_property $dash_path BtnStop onClick
[list StopMotor "NotRunning"]
# Add LED to show if Motor is running
dashboard_add $dash_path LEDRunning led G1
dashboard_set_property $dash_path LEDRunning text "Motor Running"
dashboard_set_property $dash_path LEDRunning color green_off
Question 1:
How do I organize this code (maybe into a function called Init), then how do I call it from System Console
Question 2:
When Start Motor is pressed, on click shall call a function. Should I keep the function the same file?
Question 3:
LED should be turned on by Motor-Start, turned off by Motor-Stop
Appreciate any help or advice
Thanks
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October 29, 2014, 5:01 pm
Anyone know how to automatically run a command-line script (.sh) from nios2-command-shell after a build in eclipse?
I'm looking to stream line the build process (currently I manually open the shell and execute the scripts... not fun every time!)
I use these post build scripts to generate production specific binaries.
Comments appreciated.
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October 29, 2014, 4:42 pm
I am using DE2-115 development board. I have written a verilog code where I am trying to generate a sequence of 1' and 0's using the clock frequency of 50MHz and I am getting the output as shown in the attached figure 1 below. The output should be a square wave, but this does not looks like the case, Can anyone help me on that ?
Whereas when I try to look at the signal obtained at lower frequency of 5MHz, obtained from the clock of 50 MHz, using the code to divide the clock frequency by 10 and it looks a lot like a square wave, as shown in attached figure,
20141024_143558.jpg.
Also the third figure is the signal generated of frequency 25 MHz, using clock of 50Mhz and the code written just divides the frequency by 2 and is shown in figure
20141028_133959.jpg
Can anyone helo me on why I am getting these problems of different shapes of the signal for different frequencies.
Regards
Himanshu
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October 29, 2014, 10:54 pm
i am trying to do vedic division using paravartya and nikhilam binary division..........if anyone knows code for this...pls mail to this id
abiramis5392@gmail.com
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October 29, 2014, 11:48 pm
pls anyone help me..........my project is to view movie on tv using cyclone3 embedded evaluation kit.......movie which is stored on sd card...i have demonstration like MTDB_LCD_TV...in this, output from dvd player connects to video in and line in pin in that kit...i am having all source files for that demonstrations..how to modify those files for my project..........i.e.,instead of getting seperate audio and video signals from dvd player,have to detect the sd card and read the movie files and that must be played on tv.......pls mail me if anyone knows........bhuvana.natarajan.91@gmail.com
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October 30, 2014, 6:52 am
Hello All,
I am trying to do a prototype for my new board on DE2i-150 eval board. Where I would like to run an application from SSRAM memory.
I am trying to use the reference design "DE2i_150_WEB_SERVER_MII1" provided by them along with the CD.
[
http://www.terasic.com.tw/cgi-bin/pa...o=529&PartNo=1 ]
In this reference design, if I run a memory tests on SSRAM, its failing. I tried to access SSRAM memory space from my application [running on SDRAM], I can see an unstable [Reading the same location leads to wrong different data] results from SSRAM memory space.
Is it a configuration issue for SSRAM ? or Do I have to do some changes in board/application [like make FLASH under reset while operating SSRAM - since pins are shared between SSRAM and FLASH] ?
It will be great, If anyone can give some insight for this issue.
Regards
Vinod PA
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October 30, 2014, 10:10 am
Hi,
I'm trying to use the "EDA Simulation Library Compiler" in Quartus 13.1 with ModelSIM PE 10.3c (USB dongle), but it fails with the following error..
Info: Unable to checkout a license. Vsim is closing.
Error: ** Fatal: Invalid license environment. Application closing.
Info: Unable to check out a license. Run the ModelSim Licensing Wizard from the Start->Programs menu to diagnose the problem.
Error: Compilation was NOT successful. 1 errors, 0 warnings
The license for ModelSIM is correct, and I can invoke it, and perform manual library compiles, so I know that is fine.
Any suggestions ??
Rob
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October 30, 2014, 10:50 am
Hi,
I'm a PG student, working on Xilinx Spartan 3E board. but I'm Much confused between these vendors and their board.
Please help me to understand the difference between Altera, Terrasic, Xilinx, Digilent. who are vendors. which vendors board are good for educational purpose, what are their hardware differences. is alteraa and terrasic different, please guide in this basic concept.
Thanks in advance !
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October 30, 2014, 12:18 pm
Hi, a beginner's question, when passing data from HPS to the FPGA I use the AVALON MM interface. Now I'm a bit in doubt, if it is better to check "write" and then fetch "writedata" into a reg (verilog), e.g.:
Code:
module something(
...
input write,
input [7:0] writedata,
...
);
...
reg [7:0] algo_in;
...
always @(posedge clk)begin
...
if(write)begin
algo_in <= writedata;
end
...
or if it is better to wire "writedata" directly, e.g.:
Code:
// module same as above
...
wire [7:0] algo_in;
assign algo_in = writedata;
...
Do I actually need to check "write" for an avalon mapped slave interface, I saw that in tutorials it is done. But it seems to work using wires, too?!
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October 30, 2014, 2:49 pm
Im on day 3 of my altera/nios/qsys/eclipse adventure
Ive generated an altera avalon spi/nios within qsys and have it working well. its 8 bits by default and i wanted to change that to 16 or 32 bits wide. I created copies of the altera_avalon_sp.h and altera_avalon_spi.c files (with an _32wide suffix) and saved them in the same location as the original files. I made my changes (alt_u8 to alt_u32 types), updated the .h file name in the .c source and saved everything.
I went to compile the top level source (helloworld_spi.c) and got an undefined reference to my new function.
I have tried to regenerate the bsp files, added the -lm to the nios application properties, and tried rebuilding the bsp, app project and everything that i can think of.
Can anyone help? Im an admitted newb, but i have to start somewhere...
thanks for all your help!
heres the error:
[BSP build complete]
Info: Linking helloWorld_spi.elf
nios2-elf-g++ -lm -T'../helloWorld_spi_bsp//linker.x' -msys-crt0='../helloWorld_spi_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../helloWorld_spi_bsp/ -Wl,-Map=helloWorld_spi.map -O0 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -o helloWorld_spi.elf obj/default/hello_world.o -lm
obj/default/hello_world.o: In function `main':
C:\Users\...\Desktop\jksSPI_V1\software\helloWorld _spi/hello_world.c:70: undefined reference to `alt_avalon_spi_command_32wide'
collect2.exe: error: ld returned 1 exit status
make: *** [helloWorld_spi.elf] Error 1
**** Build Finished ****
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October 30, 2014, 2:51 pm
Hi,
-- first of all, sorry, if this is a double post, my first thread concerning this issue this evening somehow never appeared in the forum ---
I am trying to get the Triple Speed MegaCore Function with PCS/PMA to come to life. I want to use the internal transceivers of my Cyclone V GX, which are hooked to 1000Base-X SFP modules, but at the moment, this things just sits there and does nothing.
- I have instantiated a TSE MegaCore function in Qsys
- I am clocking it with 125MHz, and
- I have a VHDL component, that loops through the process of byte-by-byte latching a dummy ethernet frame into the tx_d[7..0] terminals (and waiting for 9.6us) and setting tx_en appropriately before it continues to do this over and over again.
- The serial outputs and inputs are connected to the respective RX/TX outputs of the receiver banks.
From what I have read, I do not have to set any registers to "enable" the TSEs, nor do I have to configure the transceiver blocks with the altgxb manually, nor do I need a reconfiguration controller, and thus, I do not have all this stuff. However, when I look into the signal tap analyzer (or look at the physical status LEDs on the board, that are connected to the respective pins), there is no indication of activity!
Is there anything essential that I am missing? I will happily provide my design files, if someone wants to have a look at them. Also:
If someone could send me a working example for using just the PCS / PMA together with the GX transceivers on the Cyclone V, I will literally send him / her a bottle of wine and some real Swiss cheese to go with that, no matter where around the globe that is!
Cheers, Peter
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October 30, 2014, 6:25 pm
I checked all altera's devkit boards, they all didn't use this kind of channels as transceiver. They only were used as ref clock input. Our project has over used all normal transceiver channels, now we need to add a pcie-x4 interface in our system, and must release 4 used transceiver channels to implement pcie interface, and use 4 CMU channels to replace them. My question is that can we use the cmu channels as transceiver? Our speed is not very high, 2G is enough for us.
Also, someone told me that if we use that CMU channels we need design the PCS logic by ourselves. Because these CMU channels don't have PCS modules, they only have PMA compare with normal transceiver channels. Another question is how to design this PCS user logic?
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October 30, 2014, 8:51 pm
I am trying to download the DSP builder software (or Quartus II software) for 32-bit PC. Where is the link for this downloading?
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October 30, 2014, 11:44 pm
Hi,
I'm preparing design on Cyclone V with RGMII connection. I read AN 477 ("Designing RGMII Interfaces with FPGAs and HardCopy ASICs") about it and I understand what is necessary to do. I miss only one major information. It is necessary to use DQ/DQS pins on FPGA for TXD and RXD pins?
Thanks,
Milan
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October 31, 2014, 6:14 am
Hi,
We are using 5 Cyclon II FPGA (EP2C5F256) and 5 no of Serial PROM EPCS1SI8N for Every FPGA Device as per diagram.
We are the requirement to provide SPROM for every Cyclon II device and program every SPROM and Cyclone II device independently with same single header as per diagram.
In which configuration possible to our requirement? and also it will be helpful if you provide connectivity diagram..
Please give your comments as much as possible.
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October 31, 2014, 11:00 am
I am attempting to compile and run the hello world design example using the emulator on Windows 7 with Visual Studio 2013. I have AOCL and Quartus installed and the environment configured according to the quick start guide.
The host application compiles successfully using Visual Studio but when I run the executable, a message appears that says "The program can't start because altera_s5_ref_mmd.dll is missing from your computer. Try reinstalling the program to fix this problem." There is a file named altera_s5_ref_mmd.lib located in %ALTERAOCLSDKROOT%\board\s5_ref\windows64\lib but I do not see a dll. I also see the same error when I run aocl diagnose.
Additionally, I am not able to compile the kernel. When I run "aoc -march=emulator -v device/hello_world.cl", this is the output:
Code:
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected target board s5_ref
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling for Emulation ....
Error: Optimizer FAILED.
Refer hello_world/hello_world.log for details.
Here is the contents of hello_world.log:
Code:
Microsoft (R) Incremental Linker Version 12.00.21005.1
Copyright (C) Microsoft Corporation. All rights reserved.
Creating library libkernel.lib and object libkernel.exp
libkernel.obj : error LNK2019: unresolved external symbol printf referenced in function hello_world
libkernel.obj : error LNK2019: unresolved external symbol ldexp referenced in function _ZL6lengthDv4_d
libkernel.obj : error LNK2019: unresolved external symbol sinf referenced in function _Z8__tg_sinf
libkernel.obj : error LNK2019: unresolved external symbol cosf referenced in function _Z8__tg_cosf
libkernel.obj : error LNK2019: unresolved external symbol tanf referenced in function _Z8__tg_tanf
libkernel.obj : error LNK2019: unresolved external symbol sin referenced in function _Z8__tg_tand
libkernel.obj : error LNK2019: unresolved external symbol cos referenced in function _Z8__tg_tand
libkernel.obj : error LNK2019: unresolved external symbol asinf referenced in function _Z9__tg_asinf
libkernel.obj : error LNK2019: unresolved external symbol acosf referenced in function _Z9__tg_acosf
libkernel.obj : error LNK2019: unresolved external symbol atanf referenced in function _Z9__tg_atanf
libkernel.obj : error LNK2019: unresolved external symbol exp referenced in function _Z10__tg_sinhff
libkernel.obj : error LNK2019: unresolved external symbol expf referenced in function _Z10__tg_coshff
libkernel.obj : error LNK2019: unresolved external symbol logf referenced in function _Z8__tg_logf
libkernel.obj : error LNK2019: unresolved external symbol log referenced in function _Z10__tg_log10d
libkernel.obj : error LNK2019: unresolved external symbol floorf referenced in function _Z10__tg_truncf
libkernel.obj : error LNK2019: unresolved external symbol ceilf referenced in function _Z10__tg_truncf
LINK : error LNK2001: unresolved external symbol _DllMainCRTStartup
libkernel.dll : fatal error LNK1120: 17 unresolved externals
I have set %LIB% to "C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\lib".
The output of "aocl link-config" is
Code:
/libpath:C:\altera\14.0\hld\board\s5_ref/windows64/lib /libpath:c:/altera/14.0/hld/host/windows64/lib alterahalmmd.lib altera_s_ref_mmd.lib alteracl.lib acl_emulator_kernel_rt.lib pkg_editor.lib libelf.lib acl_hostxml.lib
Any assistance is appreciated.
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October 31, 2014, 11:41 am
using a Stratix IV with the SDI mega function. Trying to figure out how to insert the time code into the data stream. Anyone know how to do this?
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October 31, 2014, 1:47 pm
I use Quartus IP catalog to generate some IPs. I found since you assigned the directory where the IP should be generated, Quartus just generate all the files of the IP into the directory, it doesn't create a folder which is named by IP's name. Since there are bunch of files generated with the IP, this will be very annoying if all the files of different IPs are put in a same folder. Is therr any approach to configure the Quartus to generate each IP files in their own folder?
Thanks in advance.
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October 30, 2014, 2:27 am
Hi everybody I hope somebody can help me, I have installed the complete quartus 14.0 suite on a PC running Debian 3.16 - AMD64. So far everything including JTAG download is working except for the Modelsim (altera starter edition), when I try to run it inside quartus I get the following output in the processing tab
Quote:
Info: ************************************************** *****************Info: Running Quartus II 64-Bit Shell Info: Version 14.0.0 Build 200 06/17/2014 SJ Web EditionInfo: Processing started: Wed Oct 29 12:40:11 2014 Info: Command: quartus_sh -t /home/user/altera/14.0/quartus/common/tcl/internal/nativelink/qnativesim.tcl --rtl_sim small smallInfo: Quartus(args): --rtl_sim small small Info: Info: Start Nativelink Simulation processInfo: Info: NativeLink has detected VHDL design -- VHDL simulation models will be usedInfo: Info: Starting NativeLink simulation with ModelSim-Altera softwareError: Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.Error: Error: NativeLink simulation flow was NOT successfulInfo: Info: For messages from NativeLink scripts, check the file /home/user/VHDL/small_test/small_nativelink_simulation.rpt
Additionally a pop-up window displays this:
Quote:
Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file..Check the NativeLink log file/path/to/log/file/nativelink_simulation.rpt for detailed error messages
However if I try to run ModelSim from the bash console at modelsim_ase/linuxaloem with command "./vsim" or "xterm -e vsim" (last one acording to this
wiki) I get the following message: "Cannot find Tcl library." But the modelsim_ase contains a tcl folder and in it there is also the "tcl8.4" folder, I have tried this procedure with quartus 14.0 and 13.0 obtaining the same results.Can anyone please point me in which direction should I check to solve this issueThanks*Update: I have found that the MODEL_TECH_TCL environmental variable should point to the tcl folder, I tried that but I still get the same error, are there any more environmental variables I should set?
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