Currently, I successfully implemented the simple socket server example in DE2_115 board by using the web sever demo as a basic. One strange thing is that if I download the original web server sof file to the board and run the software elf file in Eclipse, everything works well. But, if I recompile the project in quartus 11.0 with no change, another sof file called "DE2_115_WEB_SERVER_time_limited" is generated. Also, a window says"click cancel to stop using opencore plus IP, time remaining:unlimited". I left this window open and run the software elf file in Eclipse. In the console window, the program stuck at "PHY INFO: waiting on PHY link..." and never move. It seems that the auto-negotiation is not done. This is strange because I do not change anything, both hardware in quartus and software in Eclipse. Just recompile the project in quartus and download the "time_limited" file to the board, then the function doesn't work properly. Can anyone help me to solve this problem? Thanks so much.
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problem with simple socket server implementation on DE2_115
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Test
This is a test to check how long it takes for a post to appear. It is now 9.36 am, GMt +1.
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Bit stream compression quartus II
i was working on bit stream compression architectures!!!!!!!!!!what kind of bit stream compression architecture quartus II uses where can i kind the detail
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Modelsim Error: (vcom-11) Could not find altera.maxplus2
Hello all,
I am completely new to vhdl, altera and modelsim so please bear with me if the question is too simple. I have tried to scout the web for any leads - but so far without any real progress.
I have created a simple structural design based on 74xxx components from the altera maxplus2 library (altera\13.0\quartus\libraries\vhdl\altera). I know this can be done as behavioral - but I am transferring an old TTL design that I want to verify.
I have included in my vhdl file:
LIBRARY altera;
USE altera.maxplus2.ALL;
Following setp by step the "getting started wtih quartus ii simulation using the modelsim-altera software" guide to open up modelsim with nativelink I get the following error message in the transcript window:
# ** Error: (vcom-11) Could not find altera.maxplus2.
And from this point I cannot progress. I have tried to compile the maxplus2 library with the modelsim compile functionality - but in all honesty I am not really sure what I am doing. I get a maxplus2 folder in RTL-WORK directory - but it doesnt help at all as I get the same error when I re-execute the "do"-command line.
Any pointers as to where I can look for further reading on this topic or any advice to resolve this is highly appreciated.
br /mattias
fyi: I work in msft windows environment.
I am completely new to vhdl, altera and modelsim so please bear with me if the question is too simple. I have tried to scout the web for any leads - but so far without any real progress.
I have created a simple structural design based on 74xxx components from the altera maxplus2 library (altera\13.0\quartus\libraries\vhdl\altera). I know this can be done as behavioral - but I am transferring an old TTL design that I want to verify.
I have included in my vhdl file:
LIBRARY altera;
USE altera.maxplus2.ALL;
Following setp by step the "getting started wtih quartus ii simulation using the modelsim-altera software" guide to open up modelsim with nativelink I get the following error message in the transcript window:
# ** Error: (vcom-11) Could not find altera.maxplus2.
And from this point I cannot progress. I have tried to compile the maxplus2 library with the modelsim compile functionality - but in all honesty I am not really sure what I am doing. I get a maxplus2 folder in RTL-WORK directory - but it doesnt help at all as I get the same error when I re-execute the "do"-command line.
Any pointers as to where I can look for further reading on this topic or any advice to resolve this is highly appreciated.
br /mattias
fyi: I work in msft windows environment.
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QSYS closes without ERRORs
Hi,
I'm using the latest Quartus II Subscription Edition and Qsys closes without warnings or errors when opening a qsys-project with the [Altera PLL] inside, like the [bts_ddr3_hard] example or when adding it to a new project. When the PLL is attached in the Quartus Software, outside of the Qsys, everything works fine.
One of my co-workers removed the pll from the example and i could open it, so im sure this error happens cause of this IP-Core. Are there any solutions for this bug?
Thank you for considering my request.
I'm using the latest Quartus II Subscription Edition and Qsys closes without warnings or errors when opening a qsys-project with the [Altera PLL] inside, like the [bts_ddr3_hard] example or when adding it to a new project. When the PLL is attached in the Quartus Software, outside of the Qsys, everything works fine.
One of my co-workers removed the pll from the example and i could open it, so im sure this error happens cause of this IP-Core. Are there any solutions for this bug?
Thank you for considering my request.
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DE5 cannot be recognized by lspci in Ubuntu 14.04
Hi, I just got a DE5-Net and want to do a quick test. I downloaded the PCIe_fundamental.sof, which is included in the CDROM, did a reboot but lspci showed nothing. I also tried PCIe_ImageProcess.sof but still no luck. As far as I know I should see something using lspci even without the driver. Any suggestions? Thanks.
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Cyclone III 144 QFP package forgot the ground pad on circuit board
Our circuit board guy forgot to put a ground pad on the board for the 144 pin package on the bottom of the chip. We are unable to detect it thru the JTAG port and assuming that is why. What may also be a problem is there are untented vias and traces (soldermasked though) underneath the pad of the chip. I wanted to find out if anyone else has made the same mistake and what they were able to do to repair it? Drill hole and run a wire? Pull the chip, run some copper trace tape underneath and reattach it? Any suggestions? or is it a lost cause? I think the fact that there are uncovered vias possibly shorting to the ground pad on the chip makes it total loss.
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How to create 2nd project referencing same BSP and source files?
I've created my main application and BSP using the "New Nios II Application and BSP from Template" wizard. I used the "Hello MicroC/OS-II" template because my application uses the RTOS. I've added multiple source files to my project. All of this is setup and working fine.
Now I want to create a second project for a boot program in the same workspace. The boot program will be a stripped down version of my main application. The boot program should use the same BSP and a subset of the same source files used by the main application. What is the best way to create this new project in the Nios II EDS?
If I use the "New Nios II Application" wizard I can specify the existing BSP, but there is no option for a MicroC/OS-II template. How do I configure the new project for MicroC/OS-II? Is there an easy way to copy the settings from my main application project?
How should I add the existing source files to the new project so that I don't create a new copy of the source files. I want the same source files to be referenced by the both projects so that I don't need to change the source code in two places. Is the "Link to file in the file system" Advanced option what I want to use for this? When I try this option, the New file wizard displays a warning, "file may overlap another resource. This can cause unexpected side-effects." Is this a real concern or are the "unexpected side-effects" referring to the effect that I'm going for?
Thanks for any advice.
Now I want to create a second project for a boot program in the same workspace. The boot program will be a stripped down version of my main application. The boot program should use the same BSP and a subset of the same source files used by the main application. What is the best way to create this new project in the Nios II EDS?
If I use the "New Nios II Application" wizard I can specify the existing BSP, but there is no option for a MicroC/OS-II template. How do I configure the new project for MicroC/OS-II? Is there an easy way to copy the settings from my main application project?
How should I add the existing source files to the new project so that I don't create a new copy of the source files. I want the same source files to be referenced by the both projects so that I don't need to change the source code in two places. Is the "Link to file in the file system" Advanced option what I want to use for this? When I try this option, the New file wizard displays a warning, "file may overlap another resource. This can cause unexpected side-effects." Is this a real concern or are the "unexpected side-effects" referring to the effect that I'm going for?
Thanks for any advice.
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RTL2838 device driver?
Has anybody attempted to port the RTL2838 device driver and some of the rtl apps to the SoC? I was thinking it could be a very low cost alternative to FPGA based SDR.
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Conduit(s)?
Hi, today I'm asking myself: Why do I need to use different conduits e.g. "conduit_end_0", "conduit_end_1", etc.? Or can I declare all my own signals with the same "conduit_end"? Or isn't there any difference at all?
For example, I have a simple Avalon MM Slave getting data from the HPS. The data is written to the FPGA and read from the FPGA by "writedata" with flag "write" and "readdata" with flag "read". I saw in Qsys, even the Avalon MM Slave template automatically assigns it all the name "conduit_end_0". So, is this correct, or should I create a separate "new Conduit" i.e. "conduit_end_1" for write? What happens if I create separate conduits for each signal? Is there a difference at all?
For example, I have a simple Avalon MM Slave getting data from the HPS. The data is written to the FPGA and read from the FPGA by "writedata" with flag "write" and "readdata" with flag "read". I saw in Qsys, even the Avalon MM Slave template automatically assigns it all the name "conduit_end_0". So, is this correct, or should I create a separate "new Conduit" i.e. "conduit_end_1" for write? What happens if I create separate conduits for each signal? Is there a difference at all?
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D5M Camera: VHDL Code for images acquisition on DE2-70 Board
Hi to everyone! I would like just a block for acquisition
in VHDL language, because i am programming in VHDL,
and the camera code is in Verilog . Thanks
in VHDL language, because i am programming in VHDL,
and the camera code is in Verilog . Thanks
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Installed hardware does not support device type
I'll be using Master Blaster (USB) download cable to examine/erase a program in cPLD chip P/n: EPM7192EGI160-20.
Previously used Quartus II and USB Blaster to program the chip, but Quartus does not not support EPM7192E for Examine and Erase feature.
Thus installed Max+Plus II v10.2 on winXP and driver mblaster.inf as advice.
Under programmer, I selected device EPM7192EGI160-29 but the error message
"Intalled hardware does not support device type 'EPM7192EGi60-20'" appear.
Can anyone suggest the issue.
Thanks
Previously used Quartus II and USB Blaster to program the chip, but Quartus does not not support EPM7192E for Examine and Erase feature.
Thus installed Max+Plus II v10.2 on winXP and driver mblaster.inf as advice.
Under programmer, I selected device EPM7192EGI160-29 but the error message
"Intalled hardware does not support device type 'EPM7192EGi60-20'" appear.
Can anyone suggest the issue.
Thanks
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EP4CE30F23 Fast Parallel Programming
According to the Cyclone IV Device Handbook (http://www.altera.com/literature/hb/...cyiv-51008.pdf), "FPP configuration is supported in ... all Cyclone IV E devices" (excluding the E144 package). However, when trying to convert my SOF into an RBF using "Convert Programming Files" in Quartus II 14.0.2 Build 209, I get an error:
"Device EP4CE30F23 does not supprot Passive Parallel x8 scheme"
All I can get to work is to select "1-bit Passive Serial". Is there a difference in the RBF output when selecting the different modes?
"Device EP4CE30F23 does not supprot Passive Parallel x8 scheme"
All I can get to work is to select "1-bit Passive Serial". Is there a difference in the RBF output when selecting the different modes?
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MAP is taking a day to complete
Hi,
During an FPGA image generation, the build takes an entire day in MAP phase and we are unable track in which phase it's getting stuck or taking more time. Once MAP is done, it takes another 4 hours to generate the image. Following is a transcript of MAP report :
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:29:37
.
.
.
Info (21057): Implemented 449846 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 465 input pins
Info (21059): Implemented 464 output pins
Info (21060): Implemented 7 bidirectional pins
Info (21061): Implemented 439628 logic cells
Info (21064): Implemented 8863 RAM segments
Info (21065): Implemented 2 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2692 warnings
Info: Peak virtual memory: 12386 megabytes
Info: Processing ended: Wed Oct 22 06:15:43 2014
Info: Elapsed time: 23:57:34
Info: Total CPU time (on all processors): 23:54:46
FPGA Device Used : EP4SE820F43C3 (Stratix IV)
Tool : Quartus II 64-Bit Version 14.0.0
Thanks & Regards,
Kiran
During an FPGA image generation, the build takes an entire day in MAP phase and we are unable track in which phase it's getting stuck or taking more time. Once MAP is done, it takes another 4 hours to generate the image. Following is a transcript of MAP report :
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:29:37
.
.
.
Info (21057): Implemented 449846 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 465 input pins
Info (21059): Implemented 464 output pins
Info (21060): Implemented 7 bidirectional pins
Info (21061): Implemented 439628 logic cells
Info (21064): Implemented 8863 RAM segments
Info (21065): Implemented 2 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2692 warnings
Info: Peak virtual memory: 12386 megabytes
Info: Processing ended: Wed Oct 22 06:15:43 2014
Info: Elapsed time: 23:57:34
Info: Total CPU time (on all processors): 23:54:46
FPGA Device Used : EP4SE820F43C3 (Stratix IV)
Tool : Quartus II 64-Bit Version 14.0.0
Thanks & Regards,
Kiran
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Error in tcl script
I recently downloaded modelsim 10.2 from altera.com . Whenever i try to start a new project i gett this error in tcl script.
Here is the image of the error.![]()
Please provide the required solution.
Here is the image of the error.
Please provide the required solution.
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Moving object detection using D5M/DE1-SoC
Hi,
I have implemented a video streaming design using DE1-SoC interfaced to D5M camera and VGA display. It works fine for still objects or very slowly moving objects. But if I move the object a little faster I could not see the object on VGA display.
I configured the D5M camera to export 640x480 frame and from the signal tap results it seems i am receiving more than 20 frames per second. With such a frame rate I should be able to detect moving object too. What could be the reason for that?
Is their any setting I can tweak to improve moving object detection??
Please suggest
I have implemented a video streaming design using DE1-SoC interfaced to D5M camera and VGA display. It works fine for still objects or very slowly moving objects. But if I move the object a little faster I could not see the object on VGA display.
I configured the D5M camera to export 640x480 frame and from the signal tap results it seems i am receiving more than 20 frames per second. With such a frame rate I should be able to detect moving object too. What could be the reason for that?
Is their any setting I can tweak to improve moving object detection??
Please suggest
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Cyclone V: switching between application images using altremote_update
Hi all,
I am using a Cyclone V in a custom design and I have some issues while using the altremote_update megafunction:
I have 3 different images stored in an EPCS device:
The factory image is never used in normal operation, it is only used as a fall back image when updating one of the application images has gone wrong.
I want to switch between application image A and application image B and back (the FPGA receives an external pulse signal when it should switch between the images). According to the Cyclone V Handbook, Figure 7-22, it appears that it is only possible to switch between the application images via the factory image, and not directly.
My problem is that I am only able to load one of the application images, and then switch back to the factory image. The factory image then loads the same application image as before, while the other application image is never loaded (so only image A is started every time, or only image).
In the factory image I am using logic to determine which application should be loaded. This logic is based on a Cyclone IV design, in which this setup works OK. In the Cyclone IV design, it is possible to use the READ_SOURCE port of the altremote_update megafunction to determine which boot address the previous image had been loaded from. The factory image can then use the address of the previously loaded image (for instance of image A), to switch to the other other image (in this case image).
For the Cyclone V, the READ_SOURCE port is not available in the altremote_update megafunction, so no information about previous configurations seems to be available. When I read the boot address (using the Page Select parameter) in in the factory image, it always reads back 0x000000, also when I try to write this address to another value in one of the application images.
Does anyone know whether it is possible in a Cyclone V design to still get information about the previously loaded application image? Or is the only solution to store that information in an external memory? Or is there another solution to this problem and am I trying to solve it in the wrong way?
Thanks in advance,
martenv
I am using a Cyclone V in a custom design and I have some issues while using the altremote_update megafunction:
I have 3 different images stored in an EPCS device:
- factory image, stored at 0x000000
- application image A, stored at 0x180000
- application image B, stored at 0x300000
The factory image is never used in normal operation, it is only used as a fall back image when updating one of the application images has gone wrong.
I want to switch between application image A and application image B and back (the FPGA receives an external pulse signal when it should switch between the images). According to the Cyclone V Handbook, Figure 7-22, it appears that it is only possible to switch between the application images via the factory image, and not directly.
My problem is that I am only able to load one of the application images, and then switch back to the factory image. The factory image then loads the same application image as before, while the other application image is never loaded (so only image A is started every time, or only image).
In the factory image I am using logic to determine which application should be loaded. This logic is based on a Cyclone IV design, in which this setup works OK. In the Cyclone IV design, it is possible to use the READ_SOURCE port of the altremote_update megafunction to determine which boot address the previous image had been loaded from. The factory image can then use the address of the previously loaded image (for instance of image A), to switch to the other other image (in this case image).
For the Cyclone V, the READ_SOURCE port is not available in the altremote_update megafunction, so no information about previous configurations seems to be available. When I read the boot address (using the Page Select parameter) in in the factory image, it always reads back 0x000000, also when I try to write this address to another value in one of the application images.
Does anyone know whether it is possible in a Cyclone V design to still get information about the previously loaded application image? Or is the only solution to store that information in an external memory? Or is there another solution to this problem and am I trying to solve it in the wrong way?
Thanks in advance,
martenv
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Design requires too many ram resources to fit in the selected device
Hello,
I have a design on verilog code that contains many modules.
4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a total of 2,048 bits.
the total number of memory bits used in the design is 327,680 bits (modules is used many times in the design). Although I have tried to fit my design in Cyclone III and Stratix III which has more available memory bits than what is required by the design .. I got an error "Design requires too many ram resources to fit in the selected device".
Please HELP!! Thanks
I have a design on verilog code that contains many modules.
4 modules represent ROM blocks (16 x 32-bit) that has 4-bit address, 32-bit data out. So each ROM block is 512 bits with a total of 2,048 bits.
the total number of memory bits used in the design is 327,680 bits (modules is used many times in the design). Although I have tried to fit my design in Cyclone III and Stratix III which has more available memory bits than what is required by the design .. I got an error "Design requires too many ram resources to fit in the selected device".
Please HELP!! Thanks
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OCT pin implementation in i/o assignment
Hello, i need an assistance in implementing OCT in i/o assignment editor. I had read the documents available on internet, still unable to figure it out "How to implement using Quartus II software?". Help me out, do reply if have solution for the same.
Thanks
Thanks
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Export partition netlist with blackbox
Hello,
I need to export post-synthesis netlist of entity A (all written in VHDL) as *.qxp
Deep in hierarchy of entity A there is instance entity B (written in Verilog).
The entity B should be defined when netlist of component A is used, so that component B could be defined later.
Now I have VHDL component of entity B defined in file where entity B is instantiated, but Quartus Analysis & Synthesis complaints
that I have no architecture defined for entity B (unless I actualy provide Verilog code) but I don't want to define it, I want to have blackbox there instead.
I have tried approach that I would define entity & empty architecture instead of component, but then all signals to this entity are optimized out and I don't really know how to replace it then with actual Verilog component when it is already defined as empty architecture...
Is there any way to export post-synthesis netlist with blackbox inside?
Also I need to do it automatically with TCL script, not in GUI.
Now I do this, but it does not go through the first command
Thank you
I need to export post-synthesis netlist of entity A (all written in VHDL) as *.qxp
Deep in hierarchy of entity A there is instance entity B (written in Verilog).
The entity B should be defined when netlist of component A is used, so that component B could be defined later.
Now I have VHDL component of entity B defined in file where entity B is instantiated, but Quartus Analysis & Synthesis complaints
that I have no architecture defined for entity B (unless I actualy provide Verilog code) but I don't want to define it, I want to have blackbox there instead.
I have tried approach that I would define entity & empty architecture instead of component, but then all signals to this entity are optimized out and I don't really know how to replace it then with actual Verilog component when it is already defined as empty architecture...
Is there any way to export post-synthesis netlist with blackbox inside?
Also I need to do it automatically with TCL script, not in GUI.
Now I do this, but it does not go through the first command
Code:
execute_flow -analysis_and_elaboration
create_partition -partition A -contents A
export_partition -partition A -post_fit off -post_synth on -routing off -qxp A.qxp↧