I have a design which will use gigbit transceivers, I wonder is ther an IP I can use to do Bit Error Ratio Tester to verify whether the hardware is in good shape or not?
Thanks in advance.
Thanks in advance.
↧
Is there an IP I can use to do Bit Error Ratio Tester for Gigbit transceivers?
↧
Verilog ROM code is not inferred as ROM block!!
I have written a verilog code for a ROM:
module sync_rom (clock, address, data_out);
input clock;
input [3:0] address;
output [31:0] data_out;
reg [31:0] data_out;
always @ (posedge clock) begin case (address)
///// assign values to data_out
// 0: data_out = 32'haf123412;
endcase
end
endmodule
I have also tried to add /* romstyle = "M9K" */ but when I synthesize my design the number of block memory bits is zero!! and the registers are used!! How can I force the Quartus to synthesize my code as a ROM 16 x 32-bit. I have to mention that I have changed the settings for Synthesis and Analysis to recognize the ROM and RAM of any size!
module sync_rom (clock, address, data_out);
input clock;
input [3:0] address;
output [31:0] data_out;
reg [31:0] data_out;
always @ (posedge clock) begin case (address)
///// assign values to data_out
// 0: data_out = 32'haf123412;
endcase
end
endmodule
I have also tried to add /* romstyle = "M9K" */ but when I synthesize my design the number of block memory bits is zero!! and the registers are used!! How can I force the Quartus to synthesize my code as a ROM 16 x 32-bit. I have to mention that I have changed the settings for Synthesis and Analysis to recognize the ROM and RAM of any size!
↧
↧
Strange behavour using linux
Hello,
Because im on a 32 bits windows machine, and rather not use my laptop for programming I decided to install Linux Mint 64 "As a partition" and Quartus 14.0.
This works! Alhough it seems to work. But there is one strange thing going on..
Whenever I use the programmer to program via USB, a lot of unplanned LEDS seem to sort of barely light up in the process. Nevertheless it performs its function of using the (megafunction) pll to count through its steps, and the buttons work as well. But it doesnt really feel safe. Also the Leds that are connected are seemingly performing better, more contrast so to say..
Any pointers?
Because im on a 32 bits windows machine, and rather not use my laptop for programming I decided to install Linux Mint 64 "As a partition" and Quartus 14.0.
This works! Alhough it seems to work. But there is one strange thing going on..
Whenever I use the programmer to program via USB, a lot of unplanned LEDS seem to sort of barely light up in the process. Nevertheless it performs its function of using the (megafunction) pll to count through its steps, and the buttons work as well. But it doesnt really feel safe. Also the Leds that are connected are seemingly performing better, more contrast so to say..
Any pointers?
↧
cyclone V FPGA: h2f bridge addressing
Hi,
I had another related problem with a setup between C code on Linux/HPS and the FPGA on a cyclone V SoC FPGA board. While using it via the lw_h2f bridge worked, while it didn't with the h2f bridge. I figured out I was using the wrong address.
I built my setup according to what I understand from the documentation, e.g. here
http://www.altera.com/literature/hb/...v/cv_54005.pdf
and
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/memorymap_hps.html
It says
The same in the pdf, they're talking about a base address of 0xff500000 for the h2f axi bridge. So, I thought the hint given for the 0xc0000000 for h2f of a someone here was just a mistake. I never found this address anywhere, but 0xff500000 does not work, while the undocumented 0xc0000000 works for h2f bridges. Why is that? Has the layout changed anytime? What is then the correct address for the f2h bridge, it's documented as 0xff600000, but that's probably wrong then, too?! Anybody knows?
I had another related problem with a setup between C code on Linux/HPS and the FPGA on a cyclone V SoC FPGA board. While using it via the lw_h2f bridge worked, while it didn't with the h2f bridge. I figured out I was using the wrong address.
I built my setup according to what I understand from the documentation, e.g. here
http://www.altera.com/literature/hb/...v/cv_54005.pdf
and
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/memorymap_hps.html
It says
Code:
FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge 0xFF200000
HPS2FPGA AXI Bridge Module 0xFF500000↧
uClinux using Nios II e-core
Hello Everyone,
I wanted to see if anyone has tried uClinux on Nios II e-core.?
I'm trying to run uClinux 2.6.30 on Nios II e-core. In the make menuconfig, I have turned off Hardware Multiplier option (since e-core doesn't have one). But after I download the image and try to run it, it gets stuck at
"Uncompressing Linux... Ok, booting the kernel."
Btw I'm able to run uClinux 2.6.30 on Nios II f-core.
Any help is appreciated.
Thanks,
Tedy
I wanted to see if anyone has tried uClinux on Nios II e-core.?
I'm trying to run uClinux 2.6.30 on Nios II e-core. In the make menuconfig, I have turned off Hardware Multiplier option (since e-core doesn't have one). But after I download the image and try to run it, it gets stuck at
"Uncompressing Linux... Ok, booting the kernel."
Btw I'm able to run uClinux 2.6.30 on Nios II f-core.
Any help is appreciated.
Thanks,
Tedy
↧
↧
VHDL need some help in coding
A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that implements such a system. Compile and verify the functionality of the program with appropriate test cases.
I am not really sure how to write this statement and code in VHDL
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented.
I have written the entire code but i think it is wrong
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:19 11/05/2014
-- Design Name:
-- Module Name: D2Q2Part2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity D2Q2Part2 is
Port ( D_IN : in STD_LOGIC_VECTOR (2 downto 0);
Clock: in STD_Logic;
Count : Buffer integer range 0 to 3;
Count2 : Buffer integer range 0 to 3;
Alarm : out STD_LOGIC);
end D2Q2Part2;
architecture Behavioral of D2Q2Part2 is
begin
process(Clock)
variable xnew,xold :STD_LOGIC_Vector (2 downto 0);
begin
Count <= 0;
Count2 <=2;
if Clock'EVENT and Clock ='1' then
xnew:= D_IN;
xold:= xold + "010";
if D_IN = 0 then Count2 <= Count2 +1;
if D_In /= 0 then Count2 <= 0;
if Count2 =3 then Count <=0 ; Alarm <='0';
if xnew >= xold and count <7 then Count <= Count + 1;
if Count = 6 then Alarm <= '1';
end if;
end if;
end if;
end if;
end if;
xold := xnew;
end if;
end process;
end Behavioral;
I am not really sure how to write this statement and code in VHDL
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented.
I have written the entire code but i think it is wrong
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:19 11/05/2014
-- Design Name:
-- Module Name: D2Q2Part2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity D2Q2Part2 is
Port ( D_IN : in STD_LOGIC_VECTOR (2 downto 0);
Clock: in STD_Logic;
Count : Buffer integer range 0 to 3;
Count2 : Buffer integer range 0 to 3;
Alarm : out STD_LOGIC);
end D2Q2Part2;
architecture Behavioral of D2Q2Part2 is
begin
process(Clock)
variable xnew,xold :STD_LOGIC_Vector (2 downto 0);
begin
Count <= 0;
Count2 <=2;
if Clock'EVENT and Clock ='1' then
xnew:= D_IN;
xold:= xold + "010";
if D_IN = 0 then Count2 <= Count2 +1;
if D_In /= 0 then Count2 <= 0;
if Count2 =3 then Count <=0 ; Alarm <='0';
if xnew >= xold and count <7 then Count <= Count + 1;
if Count = 6 then Alarm <= '1';
end if;
end if;
end if;
end if;
end if;
xold := xnew;
end if;
end process;
end Behavioral;
↧
aocl report: Java runtime
I'm trying to view the profiler results using `aocl report <kernel>.aocx profile.mon`
But I'm getting the following error message:
aocl report: Java runtime not installed with Quartus, please reinstall Quartus
and ensure the java runtime is included with your install.
Reinstalling Quartus didn't help. And there is java included with the install, specifically quartus/linux64/jre/bin and quartus/linux64/jre64/bin are both there.
So is some environment variable or path not set right? Where/how is it checking for java?
I've been able to do everything in the flow so far (compile and run kernels for both emulator and on the board, debug with gdb, get a profile.mon file generated, etc) so my installation shouldn't be too far off.
Any ideas?
But I'm getting the following error message:
aocl report: Java runtime not installed with Quartus, please reinstall Quartus
and ensure the java runtime is included with your install.
Reinstalling Quartus didn't help. And there is java included with the install, specifically quartus/linux64/jre/bin and quartus/linux64/jre64/bin are both there.
So is some environment variable or path not set right? Where/how is it checking for java?
I've been able to do everything in the flow so far (compile and run kernels for both emulator and on the board, debug with gdb, get a profile.mon file generated, etc) so my installation shouldn't be too far off.
Any ideas?
↧
Lpm_rom
How to implement LPM_ROM in quartus II (Block diagram approach)?
↧
I get this message "Quartus II Not fully Registered" every time I start Quartus II
I get this message every time I open Quartus II 9.1sp2 Web Edition :
================================================== ======
Quartus II Not fully Registered
Skipped: unable to execute ./bin64/jtagserver.exe --uninstall
Error: './drivers/sentinel/win_xp64/sentinst71xp64.exe /S /v"/qn"' failed with code: 1603
mount: warning: couldn't determine mount type.
mount: warning: couldn't determine mount type.
mount: warning: couldn't determine mount type.
Success: .\bin\cygwin\cygreg.bat c:\altera\91sp2\quartus\bin\cygwin
Skipped: unable to execute ./bin64/jtagserver.exe --install
================================================== ======
I'm trying to run a program on Altera DE2 Board
but only '88 88 8888' is shown on the display every time i start the .sof file in Programmer Tool
-(Which is certainly not what I am expecting- it is a timer program, the numbers should be changing every second)
I've checked the code works well on other computers.
The only difference between others' and mine was the message I get when I start Quartus II
According to the message I think something is wrong with executing jtagserver
so I did whatever google told me to do.. -installed Stand Alone Programmer program
But the message didn't go away ,
I totally don't know what's wrong .. :(
================================================== ======
Quartus II Not fully Registered
Skipped: unable to execute ./bin64/jtagserver.exe --uninstall
Error: './drivers/sentinel/win_xp64/sentinst71xp64.exe /S /v"/qn"' failed with code: 1603
mount: warning: couldn't determine mount type.
mount: warning: couldn't determine mount type.
mount: warning: couldn't determine mount type.
Success: .\bin\cygwin\cygreg.bat c:\altera\91sp2\quartus\bin\cygwin
Skipped: unable to execute ./bin64/jtagserver.exe --install
================================================== ======
I'm trying to run a program on Altera DE2 Board
but only '88 88 8888' is shown on the display every time i start the .sof file in Programmer Tool
-(Which is certainly not what I am expecting- it is a timer program, the numbers should be changing every second)
I've checked the code works well on other computers.
The only difference between others' and mine was the message I get when I start Quartus II
According to the message I think something is wrong with executing jtagserver
so I did whatever google told me to do.. -installed Stand Alone Programmer program
But the message didn't go away ,
I totally don't know what's wrong .. :(
↧
↧
How to export Qsys interrupt connections
Hello, I am using Altera Cyclone V SoC and have system connected in Qsys.
I need some way to export interrupt connections in Qsys so that I can load it in when I build a driver to know mapping of interrupts without manually typing it in.
Thank you
I need some way to export interrupt connections in Qsys so that I can load it in when I build a driver to know mapping of interrupts without manually typing it in.
Thank you
↧
OpenCL SDK can't find valid license file
I'm getting whenever I try invoke the kernel on certain build server:
I've definitely set LM_LICENSE_FILE correctly - Quartus is picking all the licenses it should, and the OpenCL SDK license is part of the same file. If I use
on the server in question, the OpenCL SDK license is reported as
The same license settings work fine on several other machines in the same subnet, and the licenses are floating (i.e. not locked to a specific MAC). I suspect there might be an issue with the shared libraries that the license lookup uses - is there a way to debug the license acquisition in more detail?
We have the Nallatech board support package installed (we have a PCIe385N-D5 board) which requires its own license - could it be related to that?
Code:
Error: aoc: Can't find a valid license for the Altera SDK for OpenCLCode:
lmutil lmstat -aCode:
Users of opencl_sdk: (Total of 5 licenses issued; Total of 0 licenses in use)We have the Nallatech board support package installed (we have a PCIe385N-D5 board) which requires its own license - could it be related to that?
↧
Arriav V FPGA doesn't work.
Hello, everyone :
I have a problem in my design. Arriav V FPGA can download successfully, but it does not work. I use combinational logic to assign 55AA in my VHDL code. After I download it to FPGA, the output of FPGA is always high. I have no idea how to fixed it !
I have a problem in my design. Arriav V FPGA can download successfully, but it does not work. I use combinational logic to assign 55AA in my VHDL code. After I download it to FPGA, the output of FPGA is always high. I have no idea how to fixed it !
↧
Error Memory in Quartus II
Hello guys!
I am trying to make a compilation of my project and I get this error:
Error (114016): Out of memory in module quartus_map.exe (4316 megabytes used)
Error (293007): Current module quartus_map ended unexpectedly
Anybody knows how to solve it?
Thanks.
I am trying to make a compilation of my project and I get this error:
Error (114016): Out of memory in module quartus_map.exe (4316 megabytes used)
Error (293007): Current module quartus_map ended unexpectedly
Anybody knows how to solve it?
Thanks.
↧
↧
Export Avalon Bus for Custom PHY
Hi,
I would like to connect the Custom PHY Megafunction to my QSYS system. Well, [rant]OK, really: first I got to get this off my chest: I think it is just so ridiculous, that Altera did not make the Custom PHY QSYS compliant by themselves - it's just a massive waste of everyone's time, come on![/rant]
So: What am I doing wrong (technically I mean, not by relying on Altera in the first place). I would attach pictures of my design, but the uploader doesn't work.
Cheers, Peter
I would like to connect the Custom PHY Megafunction to my QSYS system. Well, [rant]OK, really: first I got to get this off my chest: I think it is just so ridiculous, that Altera did not make the Custom PHY QSYS compliant by themselves - it's just a massive waste of everyone's time, come on![/rant]
- I am using the pipeline bridge to make myself a nice conduit signal outside of QSYS
- I am using word adressing
- I set the address width of the pipeline bridge to 9, which corresponds to the Address width of the Custom PHY
- Symbol width??? What's that?
- I hook the signals together
- The bus stalls (or at least that's what I think it does, because I can't find my system ID in NIOS when I do this)
So: What am I doing wrong (technically I mean, not by relying on Altera in the first place). I would attach pictures of my design, but the uploader doesn't work.
Cheers, Peter
↧
(vcom-1253) No default binding for component instance "counter : a_74161".
Hi all,
I am trying to simulate a simple counter in model sim using a counter implemented using the a_74161 counter from alteras maxplus2 library: C:\altera\13.0\quartus\libraries\vhdl\altera
Simulating the design in quartus works fine using the University Program VWF so the design appears to work - see attachment.
Trying to simulate the counter in multisim I dont get far: When I compilate my file in multisim:
vcom -reportprogress 300 -bindAtCompile -work work C:/altera/13.0/work_2/z_74161.vhd
I get:
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package maxplus2
# -- Compiling entity z_74161
# -- Compiling architecture z_74161_arch of z_74161
# ** Warning: [1] C:/altera/13.0/work_2/z_74161.vhd(66): (vcom-1253) No default binding for component instance "counter : a_74161".
# (No entity named "a_74161" was found.)
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY z_74161 IS
port ( clk: in STD_LOGIC;
ldn: in STD_LOGIC;
clrn: in STD_LOGIC;
enp: in STD_LOGIC;
ent: in STD_LOGIC;
d: in STD_LOGIC;
c: in STD_LOGIC;
b: in STD_LOGIC;
a: in STD_LOGIC;
qd: out STD_LOGIC;
qc: out STD_LOGIC;
qb: out STD_LOGIC;
qa: out STD_LOGIC;
rco: out STD_LOGIC);
END z_74161;
ARCHITECTURE z_74161_arch OF z_74161 IS
BEGIN
counter: a_74161
PORT MAP(
clk => clk,
ldn => '1',
clrn => '1',
enp => '1',
ent => '1',
d => '0',
c => '0',
b => '0',
a => '0',
qd => qd,
qc => qc,
qb => qb,
qa => qa,
rco => rco
);
END architecture z_74161_arch;
I have also compiled the C:\altera\13.0\quartus\libraries\vhdl\altera into C:\altera\13.0\work_2\simulation\modelsim\altera (see attachment).
Any help is appreciated
br /mattias
I am trying to simulate a simple counter in model sim using a counter implemented using the a_74161 counter from alteras maxplus2 library: C:\altera\13.0\quartus\libraries\vhdl\altera
Simulating the design in quartus works fine using the University Program VWF so the design appears to work - see attachment.
Trying to simulate the counter in multisim I dont get far: When I compilate my file in multisim:
vcom -reportprogress 300 -bindAtCompile -work work C:/altera/13.0/work_2/z_74161.vhd
I get:
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package maxplus2
# -- Compiling entity z_74161
# -- Compiling architecture z_74161_arch of z_74161
# ** Warning: [1] C:/altera/13.0/work_2/z_74161.vhd(66): (vcom-1253) No default binding for component instance "counter : a_74161".
# (No entity named "a_74161" was found.)
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY z_74161 IS
port ( clk: in STD_LOGIC;
ldn: in STD_LOGIC;
clrn: in STD_LOGIC;
enp: in STD_LOGIC;
ent: in STD_LOGIC;
d: in STD_LOGIC;
c: in STD_LOGIC;
b: in STD_LOGIC;
a: in STD_LOGIC;
qd: out STD_LOGIC;
qc: out STD_LOGIC;
qb: out STD_LOGIC;
qa: out STD_LOGIC;
rco: out STD_LOGIC);
END z_74161;
ARCHITECTURE z_74161_arch OF z_74161 IS
BEGIN
counter: a_74161
PORT MAP(
clk => clk,
ldn => '1',
clrn => '1',
enp => '1',
ent => '1',
d => '0',
c => '0',
b => '0',
a => '0',
qd => qd,
qc => qc,
qb => qb,
qa => qa,
rco => rco
);
END architecture z_74161_arch;
I have also compiled the C:\altera\13.0\quartus\libraries\vhdl\altera into C:\altera\13.0\work_2\simulation\modelsim\altera (see attachment).
Any help is appreciated
br /mattias
↧
Can't upload PNG
I can't upload pngs. It says invalid file!
↧
How to use Triple Speed Ethernet MAC IP with medium dependent interface?
I have a design I plan to use Altera Triple Speed Ethernet MAC IP. In the PCB, the FPGA is connected with medium dependent interface (MDI), there is no physical connection between RGMII interface with FPGA. So MDI is my only choice, in here:
http://www.altera.com/products/ip/iu..._ethermac.html
Altera mentioned it seems they support MDI since:
Serial 1.25-Gbps medium dependent interface (MDI) (optional) implemented with Altera Stratix GX-embedded serializer/deserializer (SERDES)
But in their IP configuration, there is no option to make it work with MDI. I wonder have anyone has experience using this IP work MDI?
Thanks a lot.
http://www.altera.com/products/ip/iu..._ethermac.html
Altera mentioned it seems they support MDI since:
Serial 1.25-Gbps medium dependent interface (MDI) (optional) implemented with Altera Stratix GX-embedded serializer/deserializer (SERDES)
But in their IP configuration, there is no option to make it work with MDI. I wonder have anyone has experience using this IP work MDI?
Thanks a lot.
↧
↧
Quartus II Ripping Out Logic
I'm trying to understand why Quartus is ripping out my logic. I'm trying to implement a microprocessor bus interface to an ARM based part, and I kept getting notes about being unable to find my clock pins. As I dug into it, I found it was saying that my clock input wasn't driving any logic. I've stripped everything out and have it down to a dummy piece of RTL and I'm still seeing my clock ripped out.
And the RTL viewer shows the clock and all the logic as expected (see the attachment--I can't seem to get Chrome to properly operate with an embedded image).
But when I run the compilation, I end up seeing:
Any idea what is going on?
Attached is the full log file.
(Edit: I'm using "Quartus II 64-Bit Version 14.0.2 Build 209 9/17/2014 SJ Full Version" on Kubuntu 14.04)
Code:
library ieee;use ieee.std_logic_1164.all;
entity dummy is
port
(
fpga_clk : in std_logic;
fpga_rst : in std_logic;
fpga_led_tp : out std_logic_vector(5 downto 0)
);
end entity dummy;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dummy is
signal sysrst : std_logic;
signal sysrstn : std_logic;
signal reset_count : integer range 0 to 20;
begin
rst_con : process(fpga_clk)
begin
if ( rising_edge(fpga_clk) ) then
if ( fpga_rst = '0' ) then
sysrst <= '1';
reset_count <= 0;
else
if ( reset_count < 20 ) then
reset_count <= reset_count + 1;
else
sysrst <= '1';
end if;
end if;
end if;
end process rst_con;
sysrstn <= not(sysrst);
fpga_led_tp <= (others => sysrstn);
end architecture rtl;But when I run the compilation, I end up seeing:
Info (12127): Elaborating entity "dummy" for the top level hierarchy
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "fpga_led_tp[0]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[1]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[2]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[3]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[4]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[5]" is stuck at GND
Info (17049): 5 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 2 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "fpga_rst"
Warning (15610): No output dependent on input pin "fpga_clk"
Which doesn't make any sense at all. Clearly fpga_led_tp is NOT driven by a constant, and fpga_rst and fpga_clk ARE driving logic!Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "fpga_led_tp[0]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[1]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[2]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[3]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[4]" is stuck at GND
Warning (13410): Pin "fpga_led_tp[5]" is stuck at GND
Info (17049): 5 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 2 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "fpga_rst"
Warning (15610): No output dependent on input pin "fpga_clk"
Any idea what is going on?
Attached is the full log file.
(Edit: I'm using "Quartus II 64-Bit Version 14.0.2 Build 209 9/17/2014 SJ Full Version" on Kubuntu 14.04)
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Variable Precision DSP in Arria V Devices
hey folks,
I am new to altera stuff. I am porting my design from xilinx devices to altera devices. In that process am facing problems with DSPs porting.
I am not finding dsp in altera similar to DSP48E1 to do functions like (axb) + c. I found one document Variable Precision DSP
in Arria V Devices, but not finding a way to use this in Arria v. I am using Quartus II 14.0 version(trial version). I didn't even find in Ip catalog.
Can some one help me on this.
Thanks in advance.
I am new to altera stuff. I am porting my design from xilinx devices to altera devices. In that process am facing problems with DSPs porting.
I am not finding dsp in altera similar to DSP48E1 to do functions like (axb) + c. I found one document Variable Precision DSP
in Arria V Devices, but not finding a way to use this in Arria v. I am using Quartus II 14.0 version(trial version). I didn't even find in Ip catalog.
Can some one help me on this.
Thanks in advance.
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can cyclone5 satisfy these requirements (mostly LVDS speed issues) ???
I am designing a high speed, high resolution camera for robotics vision and digital cinema, and I'm trying to figure out whether any of the cyclone5 parts are up to the design requirements. I've found answers to most of my questions in cyclone5 documentation, but haven't found answers to the following questions.
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My device will support a few different image sensors, but they all output the pixel data on 8 to 64 LVDS signals of some sort. Some signals are LVDS, others are sub-LVDS I believe (the HiSpi interface) and the data rates vary from 64 lanes at 300Mbps (CMOSIS CMV12000) to 16 lanes at 480Mbps (CMOSIS CMV20000) to 24+6 lanes at 700Mbps (aptina AR1411HS) to 8+2 lanes at 800Mbps (aptina AR1820HS). When I say something like "24+6 lanes", that means 24 LVDS pixel/data signals plus 6 LVDS clock signals (because the HiSpi interface has a separate LVDS clock for every 4 lanes of pixel/data).
As you can see, there are far too many LVDS signals to attempt to capture this data with the high-speed transceivers in the GX or GT variants of the cyclone5 FPGAs. And so, I've got to capture this LVDS data with GPIO pins. I am fairly sure that all these signals are DDR (data is captured on the rising and falling edge of the LVDS clock signals).
As a separate question, most differential signals I've read about before are "self-timing" (the clock is recovered from the data). But at least some of these image sensors output a LVDS or sub-LVDS clock for every 4 LVDS data signals. Is this supported by the FPGA, or does it expect to recover the clock from the data-signals --- which would make the FPGA operate in a way not consistent with what the image sensors expect?
Try as I might, I just can't find anywhere in the cyclone5 documents that tells me what is the fastest clock and data rates the cyclone5 GPIO receiver pairs can support to reliably read LVDS data like this. I found some information like that for the special high-speed transceivers in the GX and GT variants, but not the GPIO in any parts. This information is probably right there in front of my face (in those several thousand pages), but I don't see it. What's the answer, and where did you find this information?
-----
The device will be sending image data across 4 x 10Ge (10 gigabit ethernet) interfaces. My current idea is to interface to a quad 10GBASE-T PHY via the 32-bit XGMII interfaces. This should make the speed of those (probably non-differential) signals 10Gbps / 32 == 312.5 Mbps (presumably not DDR, but I don't have the specs on the 88x3140 or 88x3240 parts yet). So that's my next question, can the cyclone5 GPIO pins read and write at 320+ Mbps? This is another bit of information about the GPIO speeds that I cannot find (probably very close to the where the speed of LVDS signals is given). What's the answer, and where did you find this information?
-----
I was looking at the cyclone5 GT parts thinking maybe then I wouldn't need external any 10Ge PHYs. But... the more I look, the more I think that's not true. I'm guessing the cyclone5 GT parts do not transmit and receive 10GBASE-T signals, and that all the talk about 10 gigabit ethernet with cyclone5 is just marketing talk, because you still need an external PHY anyway. Am I right about this, or does the cyclone5 GT implement a 10GBASE-T PHY in the FPGA? Maybe the cyclone5 GT can send and receive data to a 10GBASE-T PHY via the XAUI interface, which is 8x narrower than the SGMII interface, but if so, that doesn't save any parts at all (just GPIO pads on the FPGA). But the cyclone5 E parts are vastly less expensive than the cyclone5 GT parts, so the bottom line is, saving a bunch of I/O pads on the FPGA is a huge waste of money. Set me straight... do I understand this correctly?
-----
I fiddled with a cyclone3 FPGA a few years ago, and was amazed they didn't make the FPGA know how to configure itself from standard 1-bit flash memory chips. Instead, you need to buy some fancy and expensive altera configuration chip, or design in an external microcontroller to fiddle pins on the flash memory chip and FPGA chip to configure the FPGA. Has this silliness been eliminated yet, or is this still the situation?
-----
Thanks to anyone who answers these questions. Getting back up to speed after so long is not easy... so many thousands and thousands of pages. Yikes!
PS: I attach 2-page fliers to the image sensor and PHY parts I mentioned above, in case that helps clarify my questions.
-----
My device will support a few different image sensors, but they all output the pixel data on 8 to 64 LVDS signals of some sort. Some signals are LVDS, others are sub-LVDS I believe (the HiSpi interface) and the data rates vary from 64 lanes at 300Mbps (CMOSIS CMV12000) to 16 lanes at 480Mbps (CMOSIS CMV20000) to 24+6 lanes at 700Mbps (aptina AR1411HS) to 8+2 lanes at 800Mbps (aptina AR1820HS). When I say something like "24+6 lanes", that means 24 LVDS pixel/data signals plus 6 LVDS clock signals (because the HiSpi interface has a separate LVDS clock for every 4 lanes of pixel/data).
As you can see, there are far too many LVDS signals to attempt to capture this data with the high-speed transceivers in the GX or GT variants of the cyclone5 FPGAs. And so, I've got to capture this LVDS data with GPIO pins. I am fairly sure that all these signals are DDR (data is captured on the rising and falling edge of the LVDS clock signals).
As a separate question, most differential signals I've read about before are "self-timing" (the clock is recovered from the data). But at least some of these image sensors output a LVDS or sub-LVDS clock for every 4 LVDS data signals. Is this supported by the FPGA, or does it expect to recover the clock from the data-signals --- which would make the FPGA operate in a way not consistent with what the image sensors expect?
Try as I might, I just can't find anywhere in the cyclone5 documents that tells me what is the fastest clock and data rates the cyclone5 GPIO receiver pairs can support to reliably read LVDS data like this. I found some information like that for the special high-speed transceivers in the GX and GT variants, but not the GPIO in any parts. This information is probably right there in front of my face (in those several thousand pages), but I don't see it. What's the answer, and where did you find this information?
-----
The device will be sending image data across 4 x 10Ge (10 gigabit ethernet) interfaces. My current idea is to interface to a quad 10GBASE-T PHY via the 32-bit XGMII interfaces. This should make the speed of those (probably non-differential) signals 10Gbps / 32 == 312.5 Mbps (presumably not DDR, but I don't have the specs on the 88x3140 or 88x3240 parts yet). So that's my next question, can the cyclone5 GPIO pins read and write at 320+ Mbps? This is another bit of information about the GPIO speeds that I cannot find (probably very close to the where the speed of LVDS signals is given). What's the answer, and where did you find this information?
-----
I was looking at the cyclone5 GT parts thinking maybe then I wouldn't need external any 10Ge PHYs. But... the more I look, the more I think that's not true. I'm guessing the cyclone5 GT parts do not transmit and receive 10GBASE-T signals, and that all the talk about 10 gigabit ethernet with cyclone5 is just marketing talk, because you still need an external PHY anyway. Am I right about this, or does the cyclone5 GT implement a 10GBASE-T PHY in the FPGA? Maybe the cyclone5 GT can send and receive data to a 10GBASE-T PHY via the XAUI interface, which is 8x narrower than the SGMII interface, but if so, that doesn't save any parts at all (just GPIO pads on the FPGA). But the cyclone5 E parts are vastly less expensive than the cyclone5 GT parts, so the bottom line is, saving a bunch of I/O pads on the FPGA is a huge waste of money. Set me straight... do I understand this correctly?
-----
I fiddled with a cyclone3 FPGA a few years ago, and was amazed they didn't make the FPGA know how to configure itself from standard 1-bit flash memory chips. Instead, you need to buy some fancy and expensive altera configuration chip, or design in an external microcontroller to fiddle pins on the flash memory chip and FPGA chip to configure the FPGA. Has this silliness been eliminated yet, or is this still the situation?
-----
Thanks to anyone who answers these questions. Getting back up to speed after so long is not easy... so many thousands and thousands of pages. Yikes!
PS: I attach 2-page fliers to the image sensor and PHY parts I mentioned above, in case that helps clarify my questions.
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