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are "symbols" or "block symbols" sorta like "personal IP" ???

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I'm trying to figure out how to create an FPGA design in a plausible manner. From centuries of hardware design with schematics, I naturally prefer to create an FPGA in schematic mode. However, I can see that a large design could easily grow so huge that I'd need a house size display to see the whole schematic at once. And scrolling a little subwindow around the entire schematic would be a terrible experience (and easy to get lost).

So the obvious idea that occurs to me is to "encapsulate" and "create my own components". For example, once I create a CRC32 subsystem in schematic mode (or get my assistant to create that subsystem in verilog), I'd want to be able to convert that CRC32 subsystem into a single "component"... which for practical purposes is a "block diagram"... which for practical purposes sorta seems similar to a "megafunction" or perhaps call it "personal IP".

The next question is, when I create them, how to I specify which signals are inputs and outputs (or bidirectional or busses), so when I later insert them as a component/subsystem into a larger "schematic" (or as a sub-component in a larger component), it appears like a rectangle with some inputs [on the left] and outputs [on the right] and control signals [on top and bottom]?

Now, I don't quite understand how this works (or if this fully works), but how is this done, and what is each component created this called in altera/quartus terminology? Would this be the same as a "symbol" or a "block symbol"?

And then, how would I insert a few of these CRC32 symbols/block-symbols/components into a design? Where would I find them and how would I insert them? Would they all appear in some "personal IP" menu somewhere once I save them? Or what?

One of the really nice things about this technique... assuming it works like I envision here... is that I could create some of these components in schematic mode, and my assistant could create some with verilog, but they'd both become components that could be dropped into a larger "schematic" or "block" AKA "block diagram".

Is a "schematic" considered the same thing as a "block diagram" in altera/quartus terminology? Is there a difference?

The next question is, can I dig down deeper into a component by double-clicking that component in the schematic or block-diagram I'm currently working in? Would it create a new window somewhere that contains the innards of that component? If so, could I edit that window to change the component? And, what if I double-click a component inside another component? Will that create yet another window, and so forth, hierarchically? That would be great, though I doubt that would be necessary very often.

Lots to understand in quartus-land. For a "schematic guy" who is not comfortable with HDL, these features would help a lot. Actually, now that I think about it, how could a pure HDL guy even deal with these [component hierarchy] issues? No, don't answer that. I don't want to know. Yet.

Fast Passive Parallel x32 for Cyclone V and FPGA configuration by the HPS

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I am referring to the link below

http://www.altera.com/literature/hb/...v/cv_54013.pdf

and with respect to this
Chapter 4-6, Table 4-1:Configuration Schemes for FPGA Configuration by the HPS

with respect to this link: http://www.altera.com/support/device...fg-matrix.html

My question is why is it that in the second link, it indicates FPPx32 by Cyclone V is not supported. But in the first link under table 4-1 shows that it is possible to configure in FPPx32? Why is there this conflict. I need to understand because the second link is consistent with the behavior in Quartus II version 14.0 and 13.1 when I try to create the rbf file, it says the mode is not support.

But then if that is the case, my biggest confusion is when working with the DE1-SoC kit, under the HPS_LED_HEX example, the rbf file is converted from the using FPPx32 compression enabled.

My 2 questions are 1: how do I convert to in FPPx32 from my sof to rbf file with Cyclone 5 device. and 2: how do I enable compression mode. Because there is no option for me to enable compression. The button to click that does not work...

Anyone encountered this issue before?

Warm Regards
CJ

GXB Receiver issue

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Hi, recently, I have an issue using Altera's GXB receivers. In my design, there are two GXB Receivers, named R0 and R1. Sometimes, the input of R1 is floating (means no GXB transmitter is connected to the input pin of rx_gxb of R1), because of which, rx_ctrldetect of R1 is undetermined, especially, its values can be 2'b00, which will result in invalid data being recognized as valid data. Is there a solution that can prevent from getting invalid data as valid data when the receiver input is floating? Thanks!

Modelsim AE launched from Quartus reports syntax error

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In the Quartus project I have a .v file declaring a set of parameters that are used in different modules.
When I launch Modelsim AE from Quartus, the compilation fails because of the error "Global declaration is illegal in Verilog 2001".
Without global declaration I have to declare the same parameter repeatedly in every .v file, which is very inefficient.

Is there anyway to workaround this problem?

help me!PC can not detect my pcie board

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I use Quartus II 13.0,Arria II GX,PCIE x4 hard IP,
most PC can detect my PCIE board,but one PC can not. no matter start or restart the PC.
the ltssm state is always 0->1->0->1->0->1->......the time of "0" is 12ms,the time of "1" is very short
never enter polling state,what should i do? can some one help me?

Cordic Reference Design

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I am looking for the code related to an263 CORDIC Reference Design.
Where is it possibile to download it?


Tx.

Stefano.

Can I use the Transceiver Toolkit for the Triple Speed Ethernet MegaCore Function ?

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Hi,

I am trying to figure out how to use the transceiver toolkit with the TSE. Is this even possible? Despite hooking everything together in QSYS, I cannot see my transceiver link, only my reconfiguration controller in the transceiver toolkit.

With the Custom PHY, I can access everything.

Cheers, Peter

Custom PHY 8b/10b test fails but 8b is OK

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Hi,

I am trying to validate my Custom PHY design with the transceiver toolkit. I am using the transceiver toolkit to generate test-patterns. My setup is very similar to the setup in The Transceiver Toolkit Example for the Cyclone V GX, only that I have 8bit symbol width and want to use 8b/10. I have serial loopback enabled, but would like to test this on gigabit hardware once it works. Without 8b/10b I can send my test-pattern and receive it without bit-errors.

As soon as I enable 8b/10b in the Custom PHY, I don't receive anything.
  1. I can't even get the receiver side to sync. It's not even receiving bit errors, it's not doing anything!
  2. Even if it would sync, I suspect that the word-alignment will not match anyhow, but I am also getting timing violations [EDIT] Harmless, see post below
    1. In the Custom PHY, I can only select one magic 10b word for alignment (OK, that's fine so far)
    2. But In the transceiver toolkit, there is only the option to have an 8b preamble word in the generator. So depending on the running disparity, I could end up with one or the other on the receiving side?
    3. In the Altera Transciever PHY IP Core User Guide, they sugggest using 1011111100 for word alignment.Where does this come from? This doesn't look like a comma symbol to me...



How do you guys test your Custom PHY with GIGE? I guess can't access the transceiver toolkit in the simulation, so that's not an option I think.

Cheers, Peter

Cyclone V SoC Rootport with MSI Ref Sys limitations

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Hello, I am trying to get the Cyclone V Rootport with MSI ref System (Ref Rocketboards) to enumerate a PCIe x4 Endpoint with no success. I have tried the Intel CT NIC which is an x1 Endpoint and it enumerates fine. Any similar experiences or known limitations to share? Thanks, Mounir

spikes in modelsim

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Hi all,

When simulating a basic counter (74161) I get spikes in modelsim – but I am unable to zoom in on those spikes in the wave window – see attachment.

When analyzing the signals I see that the spikes originates from combinations of signals; such as:

SYNTHESIZED_WIRE_22 <= SYNTHESIZED_WIRE_26 XOR SYNTHESIZED_WIRE_41

where the inbound signals SYNTHESIZED_WIRE_26 and SYNTHESIZED_WIRE_41 does not exhibit spikes; but change state at the same instance.

This phenomena occurs across many of the signals being combined.

Code attached for the simple counter circuit and its "wiring".

Any experience to share is highly appreciated.

Br /mattias
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Trouble adding additional F2H_SDRAM Port

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Hey there!
I've been working with the Quartus/Qsys environment for about 9 months now and have come across a very frustrating problem: The SECOND F2H Sdram (write-only) port I add does NOT work. The waitReq
line from the added port remains high whenever I request a burst transfer and it stays high, locking up my state machines.

The frustrating part is that the first F2H sdram port works perfectly fine, even as the second one is hung up. I followed this thread describing a similar problem:
http://www.alteraforum.com/forum/arc...p/t-41489.html

I made sure to recompile the preloader after qsys and quartus are done compiling.

The first working F2H sdram port is 32-bit (I get a warning about not using the total 64 available bits). The second, non-working port is 64 bits. (Ive changed it to 32, but that didn't work).

My design environment is split. I run quartus and qsys in Windows 7 and then I generate the pre-loader from the bsp-editor in Ubuntu Linux running in a virtual machine. I download and compile
Critical Link's uboot source instead of the stock uboot from Altera. (Could this be it?)

Any help would be greatly appreciated!

Thank you!
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Nios2 gdb and Linux

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I've been running Nios2 on Linux with success for some time and now I am trying to use gdb with no success.

I've tired the published examples but one general question persists - is the gdb stub automatically built-into
my design? I'm running from the bash command line and using the provided scripts in my makefile. I added
the '--debug' option to 'nios2-app-generate-makefile' with no success. So, I am wondering if this necessary to use gdb? Or does
the nios2-app-generate-makefile default to include a gdb stub in the build and you'd have to explicitly remove debug support.

Max 10 dual boot

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Anyone tried out the new Max 10 devices yet? They look interesting but I have hit a brick wall regarding the dual boot and remote update of the internal configuration flash.

The dual boot example works ok in that you can successfully program two simple designs into the device using the Quartus programmer but I can't create a working design that will allow self update of the internal flash.

The basic problem seems to be that if you are using the dual boot functionality, you cannot implement ram/rom content initialisation, which means it's not possible to create something like a nios core with a boot rom. So although there are dual boot and on chip flash ip blocks available in qsys, what do you drive them with?

Maybe I'm missing something - any insights appreciated.

button with fpga pull up, gnd

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I connected push button to gpio_1 pins on Altera DE2 board.
In verilog code I assigned one button pin 'r' as ouput to gnd, another pin 'c' inout tri1 (pull up).
I want to make inverter for 'c' to drive any of DE2 onboard LEDS, when button pressed LED would lit.
module link_klavos2 (q, c, r );
output q;
inout tri1 c;
output r;
supply0 gnd;
assign r = gnd;
assign q = ~c;
endmodule
In Aldec-HDL environment I got compiled, but in Quartus it wont synthesize, error:
Error (10664): Bidirectional port "GPIO_1[35]" at main3.v(35) directly or indirectly feeds itself
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fatal error - cygheap base mismatch detected ... cygwin1.dll...NiosII/Eclipse problem

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I'm trying to build and run a simple NiosII system on my DE2-115 board. I'm using Quartus II 64-bit version 14.0.0 Build 200 06/17/2014 SJ Full Version, and the corresponding Qsys and Nios II Software Build Tools for Eclipse version 14.0.0.200.
I found this Youtube tutorial, http://www.youtube.com/watch?v=HQdE3XKWykk . I went through all the steps, and everything worked until the final step. (I.e. the building of the SOPC core in Qsys worked fine, and setting the pins & compiling the project in Quartus worked fine, and programming that core onto the DE2-115 worked fine, and the target system ID matched the expected value, and the compiling/building of the simple C program in NiosII Eclipse worked fine, but the part that didn't work was the programming of the compiled/built .elf file into the DE2-115 board.) The author of the video also had the same problem at the end of the video, and he said it was because he hadn't installed Cygwin.
This is the error I get in the console (after the little dialog box popped up saying "Downloading ELF Process failed"):
0 [main] nios2-gdb-server (91992) C:\altera\14.0\nios2eds\bin\nios2-gdb-server.exe: *** fatal error - cygheap base mismatch detected - 0x612708D0/0x7F08D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version. The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution. Rebooting is also suggested if you
are unable to find another cygwin DLL.
/cygdrive/c/altera/14.0/nios2eds/bin/nios2-download: line 609: 71760 Segmentation fault nios2-gdb-server --cable 'USB-Blaster on localhost [USB-0]' --device 1 --instance 0 --sidp 0x11010 --id 0x1234 --timestamp 1415253604 --reset-target --go --tcpport none --write-pid /cygdrive/remainderofpathhere/sopctest_nov5_2014_1/software/qsys_test_nov5_2014_1/nios2-download.pid M:/remainderofpathhere/sopctest_nov5_2014_1/software/qsys_test_nov5_2014_1/qsys_test_nov5_2014_1.elf.srec

I searched my hard drive for other Cygwin installations. There was one other one in a different directory. I tried renaming all cygwin1.dll files to cygwin1_old.dll, but this had no effect on the NiosII/Eclipse programming error shown above. I also tried downloading a fresh cygwin install and replacing the Quartus/Eclipse version with the new version, but this produced a different error and didn't solve the above problem.Can anyone suggest a way to solve this problem, or point me toward a resource? Thanks in advance.

Error (12061): Can't synthesize current design -- Top partition does not contain any

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Dear Sir,

I am trying testbench code.But it seem above error.
I make clock scaler bench.
Would you tell me how to solve it?
Code is below:
testbench.v:

module clocktp;
reg clk;
reg res;
wire pre;

parameter STEP = 1000;

always begin
clk = 0; #(STEP/2);
clk = 1; #(STEP/2);
end

clk_scaler A1 (clk,res,pre);

initial begin
res = 1;
#STEP res = 0;
#STEP $stop;
end
endmodule

clock_scaler.v:

`include "defines.v"
module clk_scaler(
input clk, //clk is basic clock
input reset,
output clk_cpu
);

reg [25:0] cnt = 26'd0;

always @(posedge clk,posedge reset)
begin
if (reset)
cnt <= 26'd0;
//clk_cpu <= 0;
else if (cnt == `CPU_CLOCK) //CPU_CLOCK is 26'd49999999
cnt <= 26'd0;
else
cnt <= cnt + 26'd1;

end
assign clk_cpu = cnt < (`CPU_CLOCK / 2);

endmodule

sincerely

How to drive Global TMR clock-tree networks correctly in Altera FPGA?

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Hi,


I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with triple redundancy). As I am not interested in being locked into any vendor's automated GTMR tools, I'm looking to do this by hand. My understanding is that GTMR is required in FPGA because a single-event-upset SEU in the CRAM bits of a SRAM based FPGA could disconnect the clock tree from a large portion of the logic that it was driving...


I observe the difficulties with the following 3 approaches on an Altera Cyclone V SE:


1) Altera's Cyclone ALTPLL can generate up to 6 clock outputs from one clock source. It is technically possible to request 3 output clocks, each output clock driven at the same target frequency, duty cycle and phase offset. Unfortunately the redundancy is "optimised away" by the fitter tool, resulting in only a single global clock tree being driven. Can someone propose how to prevent this optimisation? --> Yes, it is probably better to have three ALTPLL.. please see approach 2. However, approach 1 would be interesting to explore jitter between driving registers from 3 different clock networks using this approach.


2) In true GTMR fashion, lets assume we use three input clock pins, each input clock pin driving its own pair of {ALTPLL, ALTCLKCTRL} modules. With a rather generous application of guidance to the tools (e.g. syn_keep/syn_noprune/.. like controls), it is possible to drive three global clock tree networks with 3 different PLL operating at the same speeds. I have setup a very simple timing harness (1 data input pin drives a shift register of 10 bits. Those 10 input bins are xored onto the state of 2x 10 bit shift register driving, each shift register driving one data output pin. The three shift registers are all driven by their own clock pin (pin_m?_clock)). With this simple test scheme in place, TimeQuest Timing Analyzer "setup summary" complains that:
pin_m0_clock slack: 0.650 End Point TNS: 0.000
pin_m1_clock slack: -0.877 End Point TNS: -7.575 (flagged as an error)
pin_m2_clock slack: -0.855 End Point TNS: -7.9641 (flagged as an error)
I'm not sure what is required to address these errors in a safe way.


3) If we use three input clock trees, and each clock pin directly drives its own ALTCLKCTRL module, it is possible to drive three global clock tree networks from 3 chip pins (presumably driven by a single clock source operating at the same speed). Using the same test harness described in (2) above, TimeQuest Timing Analyzer does not make any complaints. There is around -0.339 (m0_clock->m1_clock) to -0.583 (m0_clock->m2_clock) clock skew. I note that clock control for M0 and M1 are located physically close together on the middle-left-edge of the chip, where the third clock control for M2 is located on the middle-bottom edge of the chip and may explain some of the difference in skew (339 vs 583). As an related item, I implemented a single-clock version of the same test harness to check for clock-skew between registers on the same clock.. and it was down to -0.071. I'm hoping there is some way to significantly reduce that >300 skew down to something much lower. (My understanding is at least one of the primary goals of reducing the jitter between the TMR clock-trees is to prevent metastability problems on the feedback loop of TMR finite state machines [ loopback -> voter -> FSM logic -> D-FF -> loopback ].)


I'd be interested to hear advice on how to improve this (3)rd approach. I am not sure exactly what the pro's/con's of driving the global clock networks *directly* from the pins are, but it seems like approach (2) above would be better if the errors reported in (2) could be overcome.


I appreciate all input, guidance and advice on how to correctly do / optimise any of the above three manual approaches. Please feel free to propose a even better manual approach for on-chip global TMR.


Thanks


The Happy Techy

Can't Simulate NCO IP core

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Hello All.

I've run into a problem simulating the altera NCO IP core in ModelSim Altera. I've created an instantiation with the correct parameters and Quartus can compile it fine (there are a few warnings but nothing major). I've then attempted to simulate my design and I keep running into the same error.

ModelSim brings up a warning about only being able to use a single HDL language (in Altera form) and then an error that it can't find an entity. The entity that is missing has a name of [my instantiation]_ts. I've been through the files created by core gen and I can only see this as A Verilog Module in a .v file but I can't find a VHDL equivalent.

As much as Verlog is my native language I've been forced to use VHDL. I've confirmed that the simulation settings in core gen are set to give me VHDL output. I've re-run the generate just to be safe but with no luck.

Does anyone know of a solution to this, as I'm stuck without it? I'm using a slightly old version of Quartus (13) simply because I know and trust it for the platform I'm targeting. If an upgrade will defiantly cure the problem then I'm happy to do so, but as I'm weeks away from delivery I don't want to mess things about if I don't have to.

Regards, and thanks in advance

Russell

Problem with Data Integrity & Clock between 2 FPGAs

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Hi
I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end.
My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, each feeding their own logic.
In FPGA-2 there is a PLL which generates two 50 MHz clocks with 180-degree phase shift; i.e. clk2 = NOT clk1.
The clk1 feeds FPGA-2 logic. The clk2 signal goes out from FPGA-2 using a normal IO pin and feeds FPGA-1 logic through a dedicated clock pin.
FPGA-1 generates a 16-bit data using clk2 and sends it to FPGA-2.
Both FPGAs use Fast Input/Output Register on this data bus pins in order to minimize t_co & t_su.
FPGA-2 processes that data using clk1.

I used two clocks with 180 degree phase shift and I hoped that half of clock cycle is sufficient for all delays, including t_co, t_su, PCB delay, etc.

Now, using SignalTap it is evident that FPGA-1 has generated data correctly, but in FPGA-2 received data is corrupted.
What could cause this problem?
  • sending out a clock from a normal IO with Fast Output Register option enabled? Is this a good design practice?
  • Not setting IO delay constraints? Keep in mind that 50 MHz is not so high and PCB tracks are short, though with unequal lengths (less that 0.5 inch)
  • Something else ??!!!


I'm using Quartus-II v.11
My design scheme:


Thanks in advance.
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32-to-1 multiplexer VHDL CODE Simplification

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Hello! This is a code from a program and I was wondering if there was a way to simplify it with a for loop? Thank you for your help! library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; package fuggveny1 is function multi321 (A,B : in std_logic_vector) return std_logic; end fuggveny1; package body fuggveny1 is function multi321 (A,B: in std_logic_vector) return std_logic is begin if B = "00000" then return A(0); elsif B = "00001" then return A(1); elsif B = "00010" then return A(2); elsif B = "00011" then return A(3); elsif B = "00100" then return A(4); elsif B = "00101" then return A(5); elsif B = "00110" then return A(6); elsif B = "00111" then return A(7); elsif B = "01000" then return A(8); elsif B = "01001" then return A(9); elsif B = "01010" then return A(10); elsif B = "01011" then return A(11); elsif B = "01100" then return A(12); elsif B = "01101" then return A(13); elsif B = "01110" then return A(14); elsif B = "01111" then return A(15); elsif B = "10000" then return A(16); elsif B = "10001" then return A(17); elsif B = "10010" then return A(18); elsif B = "10011" then return A(19); elsif B = "10100" then return A(20); elsif B = "10101" then return A(21); elsif B = "10110" then return A(22); elsif B = "10111" then return A(23); elsif B = "11000" then return A(24); elsif B = "11001" then return A(25); elsif B = "11010" then return A(26); elsif B = "11011" then return A(27); elsif B = "11100" then return A(28); elsif B = "11101" then return A(29); elsif B = "11110" then return A(30); else return A(31); end if; end multi321; end fuggveny1;
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