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DE0-Nano NIOSII fails to compile due to license issues using free web version

November 8, 2014, 10:26 am
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In working through the demonstration applications, specifically the NIOS II processor (my first NIOS II processor), it seems as if I can not successfully compile the system.

This is on a NE0-Nano demo board I just purchased using the free version of the Quartus II version 13.0 web version.

There are no compilation errors except the following:
Error (204012): Can't generate netlist output files because the file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is an OpenCore Plus time-limited file
Error (204009): Can't generate netlist output files because the license for encrypted file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is not available
Error (204012): Can't generate netlist output files because the file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is an OpenCore Plus time-limited file
Error (204009): Can't generate netlist output files because the license for encrypted file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is not available
Error (204012): Can't generate netlist output files because the file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is an OpenCore Plus time-limited file
Error (204009): Can't generate netlist output files because the license for encrypted file "D:/altera/Projects/Third/db/ip/DE0_NANO_QSYS/submodules/DE0_NANO_QSYS_cpu.v" is not available
Error: Quartus II 32-bit EDA Netlist Writer was unsuccessful. 6 errors, 0 warnings
Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 45 warnings

I have attempted to build this using the 32 bit as well as the 64 bit version.
I know the latest version of the Quartus II software is 14, but the version 13 came with the development kit.

I am able to successful compile and download and run and debug other application I wrote and the other demonstration simpler systems.
I was wondering if this is an issue that only a full licensed version can compile the NIOS II IP that comes with the kit ?
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Can de0-nano work with high speed ADC (such as AD9283)?

November 8, 2014, 2:22 pm
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Dear Community,
I'm working in a wind meter based in DE0-NANO development board and NIOS II. Here's a basic block diagram of project:

ultrasonic signal 1 (total length of 1000 us) -> AD Converter (ad7478) sampling at 1 MSPS -> NIOS II -> Cross Correlation of these two signals -> send the result to PC
ultrasonic signal 2 (total length of 1000 us) -> AD Converter (ad7478) sampling at 1 MSPS ->

The problem is, sampling at 1 MSPS is not enough for my research project (after several prototypes, I concluded this). Some of its premises is that I must get wind measurement through cross correlation and that I must use DE0-NANO board. Therefore, sampling rate must be increased.

So, I began some tests with ad9283 adc to increase sampling rate. I tried to sample at 20 MSPS and considering the signal has a length of 1000 us, this will give me 20 000 samples.

The approach I did was to use interruption so whenever the clock's edge of AD9283 is rising, then an interruption occurs and it's time to gather ADC's data.

Unfortunately, this approach didn't work. I believe that since NIOS's clock is 50MHz and AD's clock is 20MHz, NIOS is unable to process the interruptions. I could increase NIOS clock, but I have a limitation of the SDRAM's clock I'm using (I'm using SDRAM Controller IP because of SDRAM of DE0-NANO).

Therefore, I'd like to ask for help of the experts of community whether I'm making mistakes as well as to know whether DE0-NANO is capable of working with high speed ADC, such as AD9283.

Kind Regards,
Tiago
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Unexpected output

November 8, 2014, 5:19 pm
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Frozen counter

November 8, 2014, 5:53 pm
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Hello :D,

I have spent some time trying to get the grip on Verilog by doing some counting, only the output is not quite as expected..Just a frozen on block of leds.
If someone would like to check out my Quartus file, and tell me what I did wrong i'd be much obliged.

Also why are clock signals other than std logic square waves? I can't seem to figure out why the synthesizer assigns "clocks" to them?
Attached Files
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7 segment display from 4 bit binary

November 8, 2014, 7:28 pm
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So I understand what this is supposed to be doing in theory. However in practice I can't find any practical examples. Basically I have a circuit with two 4 bit numbers in, with a switch (S) to select between the two, and the selected number is shown on the 7 segment display.
Could someone please tell me what I need to change for the syntax of this to compile?
Or alternatively if there is an easier way, I would happily use that. From all the examples I could find this seemed like the best way. currently when trying to compile this error displays for each line of the case statement

Error (10500): VHDL syntax error at test2.vhd(37) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement

Code:
ENTITY test2 IS
PORT(
    AI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    BI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    S                :IN BIT;
    S7    :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END test2;


ARCHITECTURE behavior OF test2 IS
PROCESS (AI, BI)
BEGIN


IF (S=0)
CASE "AI" is
when "0000"=> S7 <="0000001"; --1
when "0001"=> S7 <="1001111"; --2 (etc)
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100";
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
   
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;


IF (S=1)   
CASE "AI" is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100";
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
   
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
   
END PROCESS;
   


END behavior;
Thank you so much for your time
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use multiple clock drive in MAX II CPLD

November 9, 2014, 12:52 am
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I'm using my EPM1270T144C5 to implement a sinc3 filter to get my delta-sigma ADC result, and send the result to a DSP through it's external bus. As a result, I get two clock in my design one for the bus from a crystal and the other from the ADC's MCLK. Is that ok I use the two clock or I have to treat the MCLK signal as a logic input and use my high frequency clock to synchonous the MCLK signal?
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Avalon-ST - How to get the Available credit for Posted request?

November 9, 2014, 7:05 am
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I have couple of question/issues w.r.t the Avalon-ST credit management -


1) Available credit for Posted request - What is the suggested way to could control our posted requests launching based on the available credit ?


Based on the "Stratix V Avalon-ST Interface" the TX Posted data/header credit signal ( tx_cred_datafcp/tx_cred_hdrfcp ) is a credit limit ( limit stands for a static signal which only indicate the max number of credit that can be used ? ) .
http://www.altera.com/literature/ug/ug_s5_pcie_avst.pdf


Based on the "IP Compiler for PCI Express" the TX datapath provides a TX credit vector which reflects the number of available credits .
On the Avalon there is not such an interface. Can the application layer get this signal as a side band directly from the hard IP ?
http://www.altera.com/literature/ug/ug_pci_express.pdf


Based on an Example on Altera web the tx_cred_datafcp/tx_cred_hdrfcp on the Avalon interface are actually dynamic , but are inceasing when the application consume credit. So if its an "consume counter" , how can i know the credit limit?
http://www.alterawiki.com/wiki/How_C...ference_Design



2) Hard IP consumes a credit (w/ Multyple packets per cycle) -


On the 256-bit Avalon-ST we can send/receive 2 packets each cycle . Is the Hard IP can consume more then 1 header/data each cycle ?
On the Avalon description of the tx_cred_fchipcons bus , it says it can only consume one per cycle.


"During a single cycle, the IP core can consume either a single header
credit or both a header and a data credit."


Thanks
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help!!

November 9, 2014, 7:26 am
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I'm creating a code now, which i need to increase the input A,B by 2 after each state.
Example
@s0: A=00000001, B=00000010.
@s1: I want A= 00000011 and B= 00000100.
How do i do it?

And i know there's something wrong with my code, highlighted in red. As i need help for this. Can someone help?

This is code.



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.All;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity Project3M2A is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
W : out STD_LOGIC_VECTOR (7 downto 0);
X : out STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0);
LOAD : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end Project3M2A;


architecture Behavioral of Project3M2A is




type state_type is (S0,S1,S2);--,S3,S4,S5,S6,S7,S8,S9,S10);
signal state, state_next: state_type;
signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 16 downto 0);
signal mult_op0,mult_op1: signed (16 downto 0);
signal R1,R2,R3,R4,R5,R6: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 );
--signal R5,R6,R7,R8,R9,R10,R11,R12: std_logic_Vector (7 downto 0 );
signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R 9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0);
signal prod: signed (33 downto 0);
begin




P1: process(clk,rst) is
begin
if rst='0' then
state<=S0;
r1 <= (others => '0');
r2 <= (others => '0');
r3 <= (others => '0');
r4 <= (others => '0');
r5 <= (others => '0');
r6 <= (others => '0');
--r7 <= (others => '0');
--r8 <= (others => '0');
--r9 <= (others => '0');
--r10 <= (others => '0');
--r11 <= (others => '0');
--r12 <= (others => '0');
--r6 <= (others => '0');
--r7 <= (others => '0');
elsif(clk'event and clk='1') then
state <=state_next; -- next state update
r1<=r1_next;-- update next state at rising edge of clk
r2<=r2_next;
r3<=r3_next;
r4<=r4_next;
r5<=r5_next;
r6<=r6_next;
--r7<=r7_next;
--r8<=r8_next;
--r9<=r9_next;
--r10<=r10_next;
--r11<=r11_next;
--r12<=r12_next;
end if;
end process P1;
P2: process (load, state,r1,r2,r3,r4,r5,r6, A,B)
begin
r1_next<=r1;-- keep previous data if not updated
r2_next<=r2;
r3_next<=r3;
r4_next<=r4;
r5_next<=r5;
r6_next<=r6;
--r7_next<=r7;
--r8<=r8_next;
--r9<=r9_next;
--r10<=r10_next;
--r11<=r11_next;
--r12<=r12_next;
--complete<='0';
case state is
when S0 => if load ='1' then
r1_next<= signed (A(7 downto 0));
r2_next<= signed (B(7 downto 0));

state_next<=S1;
--complete<='1';
else
state_next<=S0;
end if;
when S1=>
r3_next<=signed (A(7 downto 1)& "0");
r4_next<=signed (B(7 downto 1)& "0");
state_next<= S2;
when S2=>
r5_next<=signed (A(7 downto 2)& "00");
r6_next<=signed (B(7 downto 2)& "00");
state_next<=S0;
end case;
end process p2;


end Behavioral;
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Avalon-MM Template for setting registers

November 9, 2014, 8:58 am
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Hi,

does anyone have a VHDL/Qsys template for setting registers after the board powered up? A lot of Altera IP requires to set certain configuration parameters via the Avalon-MM interface, and using the NIOS II for that seems overkill to me (and takes the smoothness out of the design flow).

Cheers, Peter
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System Console script for Avalon-MM access

November 9, 2014, 9:01 am
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Hi,

does anyone have a .tcl-script for writing data via the System Console to Avalon-MM slaves that he/she want's to share?

Cheers, Peter
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Altera memory under xilinx !

November 10, 2014, 1:15 am
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Hello everybody, So, I am trying to execute a program designed to altera but in xilinx (ISE) platform, My card is a Virtex development, and I have to use ISE, so my problem is when I run the program in ISE, it does'nt recognize the memory component ("memory_altera.png") which use altera.mf library (in attach), I thought creating the memory program in xilinx, Someone could tell me how to develop it? and what can I do about the library?

Thanks a lot, Regards,
Attached Images
Attached Files
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Problem simulating design with LPM_FF with ModelSim/Altera, works OK with QSim

November 10, 2014, 2:42 am
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Hello,

I have a problem simulating LPM_FF megafunction, I have created a project with a bdf file, containing just LPM_FF, placed pins on all inputs/outputs, set LPM_WIDTH to 4, compiled the project with no errors, generated VHDL code from bdf file, replaced bdf with the created vhd file in the same project, compiled it again with no errors, run "Analysis and Elaboration" with no errors, than run "RTL simulation" - started ModelSim / Altera, to simulate design, I apply clock and set "enable" on logic '1' rest of the signals on '0', Din[3..0] = 1010 and regardless how I set any remaining signals, the Output Q[3..0] will be shown red as "UUUU".

I have tried to simulate same design using QSim, using same simulation conditions, when I have applied logic '1' to asynchronous load pin, Din was loaded on Output - and Q[3..0] has become as expected '1010'.

Setup: QuartusII 11.1 32bit Web Edition, ModelSim Altera Starter Edition 10.1e

Any ideas about what am I doing wrong in simulating design with ModelSim Altera or using LPM_FF will be greatly appreciated !

Regards
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Nios II not installed

November 10, 2014, 3:56 am
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Dear all,
Forgive me if I should have posted this in other place?


I have this CD-disc came along when I bought the DE0-NANO FPGA, Cyclone IV E.


Please refer to the attached files.


In 2.jpg, it is stated that the free package includes "Nios II processor".


However, in 1.jpg, I could not find the "Nios II processor" component to be installed.


I tried several attempts, I could use Quartus II with no problem however, I could not locate Nios II IDE.


I also tried downloading the Nios II IDE installation file from this link (https://www.altera.com/support/softw.../dnl-nios2.jsp), however it could not be installed, it keeps prompting me that I need to have Quartus before installing Nios II, I am pretty sure I have Quartus II since I have used Quartus II and run the simulation for quite a number of times.


I am using Wondow 7, 64bit.


Please let me know:


1. how could I check if I have Nios II IDE although i don't think it is there?


2. How could I get the installation file that work along with this version of Quartus II 10.1?


Hope to hear you soon, thank you very much.


--
Attached Images
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Internal Error: Sub-system: OPT, File: /quartus/synth/opt/opt_ram.cpp, Line: 8319

November 10, 2014, 4:15 am
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Hi,
I coded a dual port ram and while synthesising it, quartus 2 is showing the following message in a dialog:

Internal Error: Sub-system: OPT, File: /quartus/synth/opt/opt_ram.cpp, Line: 8319
this->m_read_a_during_write_b_behavior == CDB_RAM_READ_OLD_DATA
Stack Trace:
0x98C32 : opt_sea_of_mux + 0x289F2 (SYNTH_OPT)
0xB8226 : MLS_SCRIPT_MANAGER::~MLS_SCRIPT_MANAGER + 0xBAF6 (SYNTH_OPT)
0x97E4E : opt_sea_of_mux + 0x27C0E (SYNTH_OPT)
0x9701C : opt_sea_of_mux + 0x26DDC (SYNTH_OPT)
0x96CDE : opt_sea_of_mux + 0x26A9E (SYNTH_OPT)

End-trace

Quartus II Version 9.0 Build 235 06/17/2009 SJ Web Edition
Service Pack Installed: 2

please note that i ve connected all ports of the RAM....

please help...
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Testing C17 with JTAG Logic.

November 10, 2014, 5:09 am
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Hi guys. Im trying to do some tests in the circuit C17 based on JTAG tecnology. But I'm having some problems with the librarys. I have this code for Xilinx FGPAs:

Code:
library IEEE;use IEEE.std_logic_1164.all;
library work;
--use work.package.all;
library selfext;
use work.gates_pkg.all;
use work.fflop_pkg.all;
but this doens't work on quartus II

Error (10481): VHDL Use Clause error at c17.vhdl(6): design library "work" does not contain primary unit "gates_pkg"
Error (10800): VHDL error at c17.vhdl(6): selected name in use clause is not an expanded name
Error (10481): VHDL Use Clause error at c17.vhdl(7): design library "work" does not contain primary unit "fflop_pkg"
Error (10800): VHDL error at c17.vhdl(7): selected name in use clause is not an expanded name
Error: Quartus II Analysis & Elaboration was unsuccessful. 4 errors, 0 warnings

How can I replace this librarys? Thank you for the help.
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.sopcinfo does not contain any CPU

November 10, 2014, 5:18 am
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i used nios II 14.0 in a computer with WIN7 to create a new project, it displays '.sopcinfo does not contain any CPU'?
i did create a cpu really!
plz help, thank you very much!
Attached Images
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MMD ERROR while connecting to board

November 10, 2014, 6:25 am
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Hi

ive got some troubles setting up an initial Hello World (for opencl) on the terasic de5net board. (windows7, 64)

the current error I get is " MMD ERROR: failed to scan for the PCI device."

this happens while "aocl diagnose" even though the driver install happend to be successful. (Error appears 16 times in a row. I suppose it goes through all the pci ports.)

Same comes up when trying to program FPGA with "aocl program" after compiling the kernel file.

Any idea what this could be? It shouldn't be a board/PCIe port problem as I ran some pci-specific example programs/designs from terasic. (Programming over quartus programmer->USB/jtag)

is the driver not well installed?? or is the mmd library not up to date? shouldnt it try to program the fpga over the usb/jtag if it fails over pcie?

Thanks for any help!
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Problem with get linux kernel source

November 10, 2014, 7:10 am
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I have got problems with “git clone … linux-socfpga.git”. The script, git_clone.sh is with Altera 14.0 as follows.

#!/bin/bash -ex
git clone http://git.rocketboards.org/linux-socfpga.git
pushd linux-socfpga && git checkout -t -b socfpga-3.13-rel14.0 origin/socfpga-3.13-rel14.0 && popd

When I run this script ./git_clone.sh from an Altera embedded command shell, it never finishes although I have bypassed the company proxy. Therefore, I can’t get the source code of Linux Kernel. I can’t carry on those examples related to Linux Kernel. Is there anything wrong with the script? Is there any other problem? Please help. Thanks
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internal error in asm module(quartus 11.1 sp2 /13.0/14.0)

November 10, 2014, 7:23 am
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Hi there,
Recently I suffered a lot from quartus II internal errors.
The error always happened in ASM module. I have tried
delelted db/incremental_db directories but it did not help.
I have tried different version quartus and it always happens.
Sometimes it disappears if I change fitter option, however
it reports error after I make several times compilation.

Below is the error reports in quartus 14.0, hope someone
have a solution. Thanks a lot!

os win7 x64 sp1, 8GB DDR3 memory,also in os win8.1 8GB DDR3 memory,ep2agx45 (also in ep2agx65)Problem Details
Error:
Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_lab.cpp, Line: 2919
num_matches == 1
Stack Trace:












0x1d358d: set_and_get_asm_qasm_accessor + 0x1c6d
0x1d7023: asm_process_sof + 0x943
0x1db033: asm_dump_re_network + 0x1873
0x1db7cc: asm_assemble + 0x3cc
0x57b2: QASM_ACCESSOR_PROXY::operator= + 0x41e2
0x10e14: qexe_get_command_line + 0x1874
0x135d9: qexe_process_cmdline_arguments + 0x599
0x136f1: qexe_standard_main + 0xa1
0x4f98: QASM_ACCESSOR_PROXY::operator= + 0x39c8
0x9678: msg_exe_fini + 0x58
0x978c: msg_exe_fini + 0x16c
0x12c4: MEM_INITIALIZER::~MEM_INITIALIZER + 0x184
0xabe9: msg_exe_main + 0x99
0x85ed: QASM_ACCESSOR_PROXY::~QASM_ACCESSOR_PROXY + 0x16ad
0x1652c: BaseThreadInitThunk + 0xc
0x2c520: RtlUserThreadStart + 0x20


End-trace


Executable: quartus_asm
Comment:
None

System Information
Platform: windows64
OS name: Windows 7
OS version: 6.1

Quartus II Information
Address bits: 64
Version: 14.0.0
Build: 200
Edition: Full Version
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depressing multisim error: # Invalid time string specified: ms

November 10, 2014, 8:26 am
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I tried to change the timings in one of the wave window dialogues to ms. I got some error messages but model sim worked as usual for a while - then suddenly it did not load stored waves formats and after a while it did not launch the wave window at all - giving me the following error message:

# Invalid time string specified: ms

Occassionaly the wave window appeared all greyed out.

No matter what project i was trying to open.

I followed an advice on another forum to delete the associated registry files which did not help.

I also uninstalled and re-installed multsim - still the same error. Now i dont even get the wave window at all and model sim is "frozen" in its transscript window.

Now I cannot use modelsim at all :cry:

Any experience on this? Any guidance is highly appreciated.

br /matttias

Here is a list of a bunch of errors lines that popped up when I still could try to add signals (which were never added)

add wave \
sim:/sync_counter_vhd_tst/clk
# Invalid time string specified: ms
# error on window .main_pane.wave - no action called registered
# Vcop::Action active_window_menu .mBar.activewindowx
# error on window .main_pane.wave - no action called registered
# Vcop::Action SetMenuState {{can_paste {Tbar::setstate_buttondirect .main_pane.wave.interior.cs.controls.tbf0.standard .tb.button_111}} {can_undo {Tbar::setstate_buttondirect .main_pane.wave.interior.cs.controls.tbf0.standard .tb.button_112}} {can_redo {.....
...etc - see attachment for continued error message
Attached Files
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