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Problem with "Set End Time" on Quartus II 13.0.

November 10, 2014, 8:33 am
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Hi everyone,

I hope you can help me with this issue. I am trying to simulate a .vwf with the 13.0 version of Quartus II and I am trying to set a "End Time" of 1ms, but when I set the end time to numbers higher than 100 us I get this error: "Invalid entry. Please enter a value between 10ns and 100us."

Do you know if there is a way to use values in the range of 1-10ms for the simulation?

Thank you in advance.
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Moving Data from FPGA to ARM side of SoCKit

November 10, 2014, 8:39 am
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Hi,

I am using 12 bits, 50 MHz LVDS ADC with Altera's SoCKit. After capturing the data from 8 channel, I want to transfer the data to ARM for further processing.

My throughput will be: 12 bits x 20MSPS(Sampling Frequency) x 8 = 1920 MSPS

Can I transfer 1920 MPSP data from FPGA to ARM side via HPS bride ? Is there any example code which helps doing this ?

I appreciate your help.

Thanks.
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Error(293007) Current module quartus_asm ended unexpectedly

November 10, 2014, 8:55 am
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I ran successfully through the fitter, but this error popped up afterwards. Any idea how to fix it? I am using Quartus II 64-bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition. I have a 64-bit Win 7 Operating System.
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How to use GPIO pins when on Linux? (DE1-SoC)

November 10, 2014, 10:50 am
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I've tried both LXDE linux and Ubuntu linux on an SD card, and I want to have UART communication through two GPIO pins with an Arduino. However, I can't find a way to access these pins in Linux. Any ideas?
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vhdl scoreboard

November 10, 2014, 11:43 am
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hello everybody. i am in my first semester of logic and design and i need some help with my final project. i am not asking you to write the entire code for my project, just some basic ground on me to start coding my project. we are using the DE1 board and have to come up with a program to run on it. i was thinking of designing some kind a score board; possibly for tennis. the scoring would be 15,30,40 and game point. there is a duece if both teams have 40. next person to get a point gains advantage. if that same person scores the next point, they win the match. bassically, you have to win by 2. i would use switches to display the scores for that match, then two different colored led's to display the amount of matches each person has one. i think a set of 3 would be sufficient. (basically who ever is the first to win 2 games) i just need help on getting a layout for this code. thanks so much guys.
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how to join 8x8bit input into 1x64bit output

November 10, 2014, 3:03 pm
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Hi,
I'm a total VHDL noob, and I feel this question is very easy, but I'm a bit under time pressure and don't want to waste too much time implementing something that is not the correct way how to do it! So far I did some shallow tutorials and, coming from software, I learned that any HDL is rather about state machine implementations, than sequential coding.

I'm playing now with the AVALON MM interface and a Cyclon V SoC FPGA board. In my C code, I have 8 bit chars which I send via /dev/mem (Linux) to the FPGA. On the other side, the FPGA puts them (writedata and write signal) into 8 bit std_logic_vectors. Here another component now needs 8x8bit chunks concatenated to a 1x64bit std_logic_vector. What is a clean VHDL way to get 8x8bit chunks from one input concatenated, and put the 1x64bit std_logic_vector into the other component's input?
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Partition Merge Error (35000)

November 10, 2014, 3:33 pm
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Hi, I originally created a design using an earlier Quartus version (11.1 SP1) which I am now trying to compile using Quartus 13.0 SP1 (the newest version I can use for Cyclone II devices). While the design had compiled fine with the older version, now I keep getting the following error:

Code:
Error (35000): Port "mod_clk~1" does not exist in the interface of the partition "Top", but another partition attempted to connect to it
Since this is a small design and I am using the WebEdition, I don't know what that "another partition" is all about - as far as I am concerned, I don't need any partitions at all.

I found the thread http://www.alteraforum.com/forum/showthread.php?t=40775 which suggests it might be a SignalTap II problem. So I disabled my SignalTap II instance, but the error still persists.

Any suggestions what I should try next?
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What is the function of "run as local c/c++ application"?

November 10, 2014, 7:07 pm
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When I finish a software project in eclipse and try to run it, I should use run as in Nios hardware. There is another option is "local c/c++ application". What does this mean? Is running the software in the computer instead of nios in FPGA?

Thanks in advance.
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High Speed Transceiver CDR Lock Time

November 10, 2014, 7:15 pm
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I am investigate the possibility that using high speed SERDES of FPGA (such as Stratix IV or V GT) to cope with burst traffice in Passive Optical Network.
In the Table 1. of Altera's Whitepaper WP-01143-1.2 "Implementing Next-Generation Passive Optical Network Designs with FPGAs", it says that CDR lock time is 267.64ns.
But in Table 1-23 of Altera's Stratix IV Device Handbook's Chapter 1, the min value of Tltd_auto is 4000ns, which is higher than the value in whitepaper.

In my opionion, Tltd_auto is equal to CDR lock time, but there have difference between the whithpaper and handbook, which value is correct?

And How to measure the CDR lock time, can anyone give me reference documents related with burst cdr lock time measurement. Thank you in advance!
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PowerPlay Early power Estimator(EPE) for Arria10 device

November 10, 2014, 9:59 pm
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Hi,
I'm working on a design incorporates an Arria10 FPGA and I want to estimate the power consumption of Arria10. But I could not find the Arria10 corresponding PowerPlay Early power Estimator(EPE) tool on the Altera's Website. I wanna ask that whether the EPE tool for Arria10 is not avaliable for now and will it be avaliable in the near future.

Another question is that without the EPE tool, how can I estimate the FPGA power consumption at the beginning of a design? How about to creat a Quartus project and write some impractical verilog files while using like 70% RAM,DSP,IO.etc resources and run the PowerPlay Power Analyzer in Quartus to estimate the power consumption of the FPGA?

Thankyou！ :)
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Warning (13004): Presettable and clearable registers converted to equivalent circuits

November 10, 2014, 4:02 pm
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Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

There are a few components impacted by this warning. Doing a search on the Altera Site, this is what it has to say:

CAUSE: One or more registers in the design have one of the following conditions:

  • The register has both a preset and a clear signal.
  • The register has a preset signal but does not have a clear signal, and Analysis & Synthesis turned off the NOT Gate Push-Back logic option.
  • The register has an asynchronous load and corresponding data signal.

The current device family does not support any of these conditions. As a result, Analysis & Synthesis converts the register to equivalent circuits with a latch, a register and logic, and the resulting register powers-up to an undefined state (X). In addition to that, DEV_CLRn places the register in an undefined state, and the resulting circuit is prone to glitches because the there are different paths from the asynchronous signals to the output of the logic representing the register. Since these paths have different delays, glitches can occur, especially if the asynchronous signals are coming from combinational logic, or if the register is feeding combinational logic. See submessages for details.
ACTION: No action is required. If you want to prevent glitches, put KEEP attributes on the asynchronous signals that feeds the register, and on the register itself. This action is necessary only if the asynchronous signals come from combinational logic or if the register feeds combinational logic. Make sure that you perform timing simulation to verify that no unexpected glitches occur.


The main component impacted (largest number of originating warnings) is a 16-bit shift register with asynchronous load. An AND gate feeds the Load Signal. I put a /* synthesis keep */ on the load line but this did not resolve the issue. Any suggestions on this?
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where could I find the nios-linux-20120621.tar , the Wiki link is out of work

November 10, 2014, 7:01 pm
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DE2-70 Verilog SDRAM Controller

November 10, 2014, 8:53 pm
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Hi All,

Looking through the forums here I see that this question has been asked a lot, but I am struggling to actually find an answer to it.

I have a DE2-70 development kit (Cyclone II EP2C70 device) which has rwo ISSI IS42S16160B devices on it (32MB x2 SDRAM).

I would like to use these two SDRAM chips (actually 1 would be sufficent, but anyway) from my verilog custom logic. Understandably, I need an SDRAM controller and this is not something that I want to try implementing myself.

I have been scouring these forums and google for a couple of days now looking for a solution, but so far I am largely coming up empty.

I found the SDR SDRAM Controller reference design from Altera. However this seems to be for an older Cyclone development kit and is using a different SDRAM device. I am not sure if this would be a drop-in replacement or not (and if not, I have no idea how much would need to be modified to suit the devices I have available). Can anyone shed some light on to this?

I also found the 4-port SDRAM controller from one of the Terasic examples. As of yet, I have not managed to find any documentation to accompany this though. Does anyone happen to know if any documentation exists for this?


Just to make it a little clearer.
I do not want to use NiosII.
I do not want to use Qsys.
I do not want to use the SoPC builder.
I want to avoid using the Avalon-MM (and Avalon-ST) interfaces if at all possible (this will be the only component in the entire system that would be using it).

Also, why does Altera not provide an SDR SDRAM IP MegaFunction core?

Best Regards
Bidski
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PowerPlay Early power Estimator(EPE) for Arria10 device

November 11, 2014, 2:08 am
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Hi,
I'm working on a design incorporates an Arria10 FPGA and I want to estimate the power consumption of Arria10. But I could not find the Arria10 corresponding PowerPlay Early power Estimator(EPE) tool on the Altera's Website.
http://www.altera.com/support/device...er%20Estimator
I wanna ask that whether the EPE tool for Arria10 is not avaliable for now and will it be avaliable in the near future.

Another question is that without the EPE tool, how can I estimate the FPGA power consumption at the beginning of a design? How about to creat a Quartus project and write some impractical verilog files while using like 70% RAM,DSP,IO.etc resources and run the PowerPlay Power Analyzer in Quartus to estimate the power consumption of the FPGA?

Thankyou！ :)
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PLL driving ALTCLKCTRL routing CYCLONE IV E

November 11, 2014, 2:52 am
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Hi Folks,

-Cyclone IV E

I have a PLL whose output I feed to an ALTCLKCTRL IP with an enable, the output of which feeds a CLK output pin on the device.

When compiling I get the following warning:

Warning (15064): PLL "altpll1:b2v_inst1|altpll:altpll_component|altpll1 _altpll1:auto_generated|pll1" output port clk[0] feeds output pin "SMA_CLKOUT~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance


I dont see this warning when I leave out the CLKCTRL and therefore just feed the output directly to an PLL output (SMA_CLKOUT in above msg)

What do I need to do to the routing to ensure that i can pass the PLL output through the CLKCTRL and to the PLL output pin without reducing performance?

I have had a look at the assignments page, but I am a little uncertain what I need to set up, playing around with it just seems to result in unknown nodes (question marks)...

many thanks for any advice
David
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Find parameter names on an an entity

November 11, 2014, 5:23 am
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Hi,

can someone please tell me how to find the (internal?) parameter names that Quartus uses?

For example, when I was looking for help with creating clocks for TimeQuest for an LPM_Counter, I was pointed to things like :
{lpm_counter0:Clock_Divider|lpm_counter:LPM_COUNTE R_component|dffs[4]} as the clock target
Where lpm_counter0 is a custom LPM counter type
Clock_Divider is the instance name
And dff[4] is the port that I want to write the counter to.

However, I don't know how I could have found this for myself.
The LPM_Counter has ports name CLK and q[0..x], it turns out that dffs[4] is equivalent to q[4], but how would I know that?
Where is dffs[] defined?

My specific problem at the moment is that I have an input pin that is used in a small piece of custom VHDL.
The output from the VHDL block is used as the clock input for a 74273 function block
TimeQuest identifies the input pin name as a clock signal that I need to create a clock for.
So, I assume that I need to create a clock for the CLK port of the 74273

Using the Counter example, I guess that I need something like the
Block type (74273?) : Instance Name | [some attribute name][some index name]?

Is there a Quartus manual or help file that tells me how I can find parameter names on blocks that are different to those shown on the parameters/pins display?

regards
Dave
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VERILOG LCELL Simulation

November 11, 2014, 7:37 am
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I have implemented a ring oscillator using LCELLs. I am able to simulate it using ModelSim-Altera with the following VHDL statement:

genvar i;
generate for (i=0; i<NUM_LUTS-1; i++)
begin : lut_ring
// ALTERA BUG: LCELL must be lowercase for simulator
(* keep *) lcell lcell_inst (
.in ( lut_wire[i] ),
.out ( lut_wire[i+1] )
);

lut_ring(0) <= lut_ring(NUM_LUTS-1) xor not(constq) after 1.702ns;

Simulation shows an oscillating output.

I have written the same code in Verilog.

assign lut_wire[0] = lut_wire[NUM_LUTS-1] ^ ~constant;

How do you simulate it? If I put a #1.702 after the ASSIGN it doesn't work!

Thanks.
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Flash Configuration Error LED

November 11, 2014, 8:26 am
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Hello,

I am using the Arria V starter board. After programming to flash memory at address 0x100000 the "D10 Error LED" lights up when "the FPGA configuration from flash memory fail".
I am still able to program my system and download software to Nios cores, the program runs properly, and the Flash memory contents are correct.

Something obviously does go wrong during start up because usually the LED display shows "Not connected" but now it is a bunch of black boxes.When I reset flash memory everything is fine.
Is this big a deal? How do I know what part of flash I can safely overwrite?

I am not using the whole flash device and have set the upper address bits to zero (only the range 0x0-0x400000). Is this region of flash not usable?

Thanks
Jonah
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what does tri1, tri0

November 11, 2014, 10:32 am
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How tri1 and tri0 are implemented in quartus II. Can't understand results from synthesized code;


module main3 (cols,LEDG,rows) ;

// ------------ Port declarations --------- //
input tri0 [3:0] cols;

output reg [3:0] rows;
initial begin rows = 4'b1111; end
// -------- Component instantiations -------//
output wire [3:0] LEDG;

assign LEDG = cols;

endmodule

Rows and cols are gpio pins which are floating, not connected to anything (GPIO_1 DE2 board).
Result: LEDG[3:0] are lighting, how can cols have HIGH level when they should be pull downed?
I can even turn off LEDG by touching one finger pins and other finger SD card metalic case on board which is grounded. So there are negligible voltage and no pull down I think. If there would be any pull down implemeted how should RTL schema look like ( I attach this code RTL schema).
Attached Images
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Max 10

November 11, 2014, 12:53 pm
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Hello!

Does anyone know when will altera provide support for MAX 10 SA series FPGA? I cant find any BSDL file, package dimmension, early power estimator and many more. Why did they release device without support?
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