library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vgaController is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
video_on : out STD_LOGIC;
p_tick : out STD_LOGIC;
pixel_x : out STD_LOGIC_VECTOR (9 downto 0);
pixel_y : out STD_LOGIC_VECTOR (9 downto 0));
end vgaController;
architecture Behavioral of vgaController is
-- VGA 640 -by - 480 sync p a r a m e t e r s
constant HD: integer:=640; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace "Sync Pulse"
constant VD: integer:=480; -- vertical display area
constant VF: integer:=10 ; -- v. front porch
constant VB: integer:=33 ; -- v. back porch
constant VR: integer:=2 ; -- v. retrace "sync pulse"
-- mod-2 counter
signal mod2_reg, mod2_next : std_logic;--mod-2 counter to generate the 25-MHz enable tick
-- sync counters, two counters for the horizontal and vertical scans
signal v_count_reg, v_count_next : unsigned(9 downto 0);
signal h_count_reg, h_count_next : unsigned(9 downto 0);
--To remove
--potential glitches, output buffers are inserted for the hsync and vsync signals. This leads
--to a one-clock-cycle delay. add a similar buffer for the rgb signal in the pixel
--generation circuit to compensate for the delay.
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next ,h_sync_next : std_logic;
--status signal
signal h_end , v_end , pixel_tick: std_logic;
begin
--register
process(clk,reset)
begin
if (reset='1') then
mod2_reg <='0';
v_count_reg <=(others=>'0');
h_count_reg <=(others=>'0');
v_sync_reg <='0';
h_sync_reg <='0';
elsif(clk'event and clk='1')then
mod2_reg <=mod2_next;
v_count_reg <=v_count_next;
h_count_reg <=h_count_next;
v_sync_reg <=v_sync_next;
h_sync_reg <=h_sync_next;
end if;
end process;
--mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg = '1' else '0';
--status
h_end <= --end of horizonal counter
'1' when h_count_reg = (HD+HF+HB+HR-1) else --799
'0';
v_end <= --end of vertial counter
'1' when v_count_reg = (VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process(h_count_reg,h_end,pixel_tick)
begin
if (pixel_tick='1') then --25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg+1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mode-525 vertical sync counter
process(v_count_reg,h_end,v_end,pixel_tick)
begin
if (pixel_tick='1' and h_end='1') then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg+1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertial sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg >= (HD+HF)) --656
and (h_count_reg <= (HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg >= (VD+VF)) --490
and (v_count_reg <= (VD+VF+VR-1)) else --491
'0';
--video on/off
video_on <= '1' when (h_count_reg < HD) and (v_count_reg < VD) else '0';
--output signals
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end Behavioral;library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;entity ttl_finder is port( clk, ena, sal_ttl : in std_logic; sal_1, sal_2 : out std_logic; sal_f : out std_logic_vector(3 downto 0));end entity;architecture ttl_tester of ttl_finder issignal cont : std_logic_vector(1 downto 0) := "00";signal results : std_logic_vector(3 downto 0) := "0000";beginprocess(clk, ena)variable c : std_logic;variable d : std_logic;variable e : std_logic;beginif ena = '1' then if cont < "11" then sal_1 <= cont(0); sal_2 <= cont(1); if rising_edge(clk) then results(conv_integer(cont)) <= sal_ttl; end if; cont <= cont + 1; else sal_1 <= cont(0); sal_2 <= cont(1); if rising_edge(clk) then results(conv_integer(cont)) <= sal_ttl; end if; cont <= "00"; end if;end if;end process;sal_f <= results;end ttl_tester;