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Multiplexer testbed simulation/ Quartus II 13.0 64 bit????

January 3, 2015, 10:47 am
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Hello there,

I am currently trying to run a testbed simulation of a multiplexer using Quartus II 13.0 64 bit, I followed all the procedures to generate waveforms in conjunction with ModelSim-Altera but there seemed to be a problem with my code. It says: Error (10482): VHDL error at tb_NAME.vhd(83): object "a" is used but not declared

Here is my full code:

Vhdl Test Bench template for design : NAME
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY NAME_vhd_tst IS
END NAME_vhd_tst;
ARCHITECTURE NAME_arch OF NAME_vhd_tst IS
-- constants
-- signals
SIGNAL d0 : STD_LOGIC;
SIGNAL d1 : STD_LOGIC;
SIGNAL d2 : STD_LOGIC;
SIGNAL d3 : STD_LOGIC;
SIGNAL f : STD_LOGIC;
SIGNAL s0 : STD_LOGIC;
SIGNAL s1 : STD_LOGIC;
COMPONENT NAME
PORT (
d0 : IN STD_LOGIC;
d1 : IN STD_LOGIC;
d2 : IN STD_LOGIC;
d3 : IN STD_LOGIC;
f : OUT STD_LOGIC;
s0 : IN STD_LOGIC;
s1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : NAME
PORT MAP (
-- list connections between master ports and signals
d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
f => f,
s0 => s0,
s1 => s1
);
init : PROCESS
-- variable declarations

BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations


BEGIN

-- code executes for every event on sensitivity list

a<='0';
b<='0';
wait for 50ns;
a<='1';
b<='0';
wait for 50ns;
a<='0';
b<='1';
wait for 50ns;
a<='1';
b<='1';
wait for 50ns;
a<='0';
b<='0';
wait for 50ns;


WAIT;
END PROCESS always;


BTW, understand I have to declare variable, I'm just not sure how!!!

Tanks in advance
END NAME_arch;
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how to sent 5 different data in 5 five clock cycles

January 4, 2015, 2:31 am
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Hello everyone

I need to sent 5 different 16 bits data in 5 five clock cycles to my costum component.
My Altera board is driven by a 50MHz oscillator (a period of 0.02 µs).

so should I write

IOWR_16DIRECT(BASE , OFFSET, DATA_1);
usleep(0.02);
IOWR_16DIRECT(BASE , OFFSET, DATA_2);
usleep(0.02);
.
.
.
IOWR_16DIRECT(BASE , OFFSET, DATA_5);
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components base address and offsets

January 4, 2015, 2:45 am
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I know how to get the base address of each component in a NIOS II system "Qsys" or the "system.h" file.

What I dont understand is what is the offset and how to get it.

for example component's base address starts at 0x0000 and ends at 0x0001, does this represents a 32bits line and the offset is the index of the byte to read ?

If that the case, how do I know how the bytes are mapped to the component pins ? ( writedata is the first or the second ... ?)
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VIP format

January 4, 2015, 7:21 am
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hello there, Happy new year.

I am studying VIP suite and avalon-ST stream data.

as far as I read data format of Video stream of VIP suite, it describes only one pixel ( at most ).
you can specify bit-width, but still for one-pixel.
I tested with test-pattern-generator core.

I want to send paralleled data, via avalon-ST.

I do know I can send multiple bit data via avalon-ST as many as I want.
but I am wondering if those data are illegal as VIP suite format.

could somebody give me a hint?
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-O3 and --util options deprecated

January 4, 2015, 7:56 am
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Hi,

In the release notes for 14.1, it says the -O3 and --util <N> options have been deprecated. Why?

If I try to use them, the compiler output on the command line seems to show they still work.

Thanks,

Smith
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Issue Of legacy interrupt in pcie HARD_IP

January 4, 2015, 8:46 am
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hi,
we are using altera Pcie hard ip (stratix-4GX).
We have generated an interrupt using legacy i.e in hard ip we have controlled an interrupt using app_int_req,app_int_ack variables In hard ip.
we are using Dell 6850 server with linux Os. when we are working with single pcie card our functionality working properly but when we are working with two pcie cards in same server we are getting issue of Non Maskable interrupt and system is going to hang.
please help us how to handle this issue.
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Legacy interrupt issue in pcie hard_ip

January 4, 2015, 8:49 am
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hi,
we are using altera Pcie hard ip (stratix-4GX).
We have generated an interrupt using legacy i.e in hard ip we have controlled an interrupt using app_int_req,app_int_ack variables In hard ip.
we are using Dell 6850 server with linux Os. when we are working with single pcie card our functionality working properly but when we are working with two pcie cards in same server we are getting issue of Non Maskable interrupt and system is going to hang.
please help us how to handle this issue.
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Tse mac

January 4, 2015, 8:55 am
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I am using ALTERA tripple speed ethernet ip core.My question is:-If rx_section_empty has crossed its threshold value and not coming down,will TSE MAC keep on sending pause frames ?????
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System Console and monitor service

January 4, 2015, 12:33 pm
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I'm testing the monitor service from system console.

Below the example code (from help in system console) with modified registers. 0x00004014 is a register with is changing at 2 hz and 0x00004024 at 1 hz. With some C code I verified that the registers are indeed changing.

Code:
#
# Get monitor service
#
set service_path [get_service_paths monitor]

#
# Claim a monitor service
#
set monitor_path [claim_service monitor $service_path "my_lib" ""]

# Assume there is one device and one master
set master_path [lindex [get_service_paths master] 0]

#
# Define monitor service properties
#
monitor_set_interval $monitor_path 100

monitor_set_callback $monitor_path
[list example_callback_proc $monitor_path $master_path]

#0x00004010 | 0x00004020 | 0x00004030 | 0x00004040


monitor_add_range $monitor_path $master_path 0x00004014 1
monitor_add_range $monitor_path $master_path 0x00004024 1

#TCL callback procedure for the monitor service
proc example_callback_proc {monitor_path master_path} {
  set w1 [monitor_read_data $monitor_path $master_path 0x00004014 1]
  set w2 [monitor_read_data $monitor_path $master_path 0x00004024 1]
  set i1 [monitor_get_read_interval $monitor_path $master_path 0x00004014 1]
  set i2 [monitor_get_read_interval $monitor_path $master_path 0x00004024 1]

  puts "0x00004014: $w1 ($i1 ms) 0x00004024: $w2 ($i2 ms)"
}

#
# Activate the monitor service
#

monitor_set_enabled $monitor_path 1
I expect something like:
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)


But I get:
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x01 (100 ms) 0x00004024: 0x01 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)
0x00004014: 0x00 (100 ms) 0x00004024: 0x00 (100 ms)

As you can see, the 0x00004024 is a copy of 0x00004014. I now for sure the values of the register are correct and changing.

I tested this two way's, one with an C application and two with system console with 20 bytes read on the callback function.

Output of C:
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x01 0x00004024: 0x00
0x00004014: 0x01 0x00004024: 0x00
0x00004014: 0x01 0x00004024: 0x00
0x00004014: 0x01 0x00004024: 0x00
0x00004014: 0x01 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x01
0x00004014: 0x00 0x00004024: 0x01
0x00004014: 0x00 0x00004024: 0x01
0x00004014: 0x00 0x00004024: 0x01
0x00004014: 0x00 0x00004024: 0x01
0x00004014: 0x01 0x00004024: 0x01
0x00004014: 0x01 0x00004024: 0x01
0x00004014: 0x01 0x00004024: 0x01
0x00004014: 0x01 0x00004024: 0x01
0x00004014: 0x01 0x00004024: 0x01
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00
0x00004014: 0x00 0x00004024: 0x00


Code:
monitor_add_range $monitor_path $master_path 0x00004014 20

#TCL callback procedure for the monitor service
proc example_callback_proc {monitor_path master_path} {
  set w1 [monitor_read_data $monitor_path $master_path 0x00004014 20]
  set i1 [monitor_get_read_interval $monitor_path $master_path 0x00004014 20]

  puts "0x00004014: $w1 ($i1 ms)"
}
Output of system console with change of size in read action:
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)
0x00004014: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (100 ms)

From the documantion: "More ranges can be added. with monitor_add_range". This is also shown in the example. So I don't understand why this is not working.

Do some of you have an idea?
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NIOS II v14.1 Unresolved System Includes

January 4, 2015, 1:54 pm
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I have several NIOS II C projects that after upgrading to 14.1 will not compile. All the system include files are marked "unresolved inclusion".

I noticed when I go into the properties -> C/C++ General -> Paths and Symbols, in the Languages column there are two entries for each
language. There are two "GNU C" entries but the first entry has no include directories. The second GNU C entry seems to have the correct
include directories, but I think it is getting ignored and the first blank entry is being used instead.

I can make it work if I manually add the same directories to the blank GNU C entry, but that is a tedious task to do for every NIOS project.

Has anyone else had this problem and found a more elegant solution?
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Gate Level Simulation - Can't launch ModelSim-Altera

January 4, 2015, 8:58 pm
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Hi all

I'm having some difficulty using Modelsim from within Quartus II 14.0 on my linux 64 bit system. Whenever I attempt perform gate level simulation I get the following error from the console:

Error: Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
Error: Error: NativeLink simulation flow was NOT successful
Info: Info: For messages from NativeLink scripts, check the file /home/jeremy/altera/14.0/mem_test_nativelink_simulation.rpt

Please note that the EDA tools path is configured correctly. The native link script details the following:

Code:
Info: Start Nativelink Simulation process

========= EDA Simulation Settings =====================

Sim Mode              :  Gate
Family                :  cycloneive
Quartus root          :  /home/jeremy/altera/14.0/quartus/linux64/
Quartus sim root      :  /home/jeremy/altera/14.0/quartus/eda/sim_lib
Simulation Tool      :  modelsim-altera
Simulation Language  :  vhdl
Version              :  93
Simulation Mode      :  GUI
Sim Output File      :  mem_test.vho
Sim SDF file          :  mem_test__vhdl.sdo
Sim dir              :  simulation/modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /home/jeremy/altera/14.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File mem_test_run_msim_gate_vhdl.do already exists - backing up current file as mem_test_run_msim_gate_vhdl.do.bak7
Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
Error:
Error: NativeLink simulation flow was NOT successful



================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  NONE
Nativelink TCL script failed with errorInfo:  Can't open transcript file msim_transcript
    invoked from within
"if [catch { open "msim_transcript" r } tscr_fid] {
            nl_postmsg error "Error: Can't launch $tool Simulation software -- make sure the software is pro..."
    invoked from within
"if [ catch {eval gen_msim_script args_hash} msim_do_file_name] {
    error "$::errorCode" "$::errorInfo"
    } elseif {$script_mode == 0} {
    post_message..."
    (procedure "launch_sim" line 109)
    invoked from within
"launch_sim launch_args_hash"
    ("eval" body line 1)
    invoked from within
"eval launch_sim launch_args_hash"
    invoked from within
"if [ info exists ::errorCode ] {
                set savedCode $::errorCode
                set savedInfo $::errorInfo
                error $result $savedInfo $savedCode
            } else {
            ..."
    invoked from within
"if [catch {eval launch_sim launch_args_hash} result ] {
            set status 1
            if [ info exists ::errorCode ] {
                set savedCode $::errorCode
                set sav..."
    (procedure "run_sim" line 78)
    invoked from within
"run_sim run_sim_args_hash"
    invoked from within
"if [ info exists ::errorCode ] {
            set savedCode $::errorCode
            set savedInfo $::errorInfo
            error "$result" $savedInfo $savedCode
        } else {
            er..."
    (procedure "run_eda_simulation_tool" line 330)
    invoked from within
"run_eda_simulation_tool eda_opts_hash"
I'm assuming this may be a permissions issue but I can't seem to resolve it. I think the msim_transcript is dynamically generated. Can anyone help me with this issue?
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Quartus 14.1 burning epcs（nios）

January 4, 2015, 11:16 pm
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Recently, my company in the debug nios.Probably as follows:



Software version：quartus 14.1

device：EP4CGX110DF31C7。

epcs：MICRON : N25Q064A13ESE40F


The problem：

On the FPGA curing, burning is not successful（*.sof Can download properly，Nios debugging to normal）

log：

Info: EPCS identifier is 0x20BA17

Info: :confused: - looking for section [EPCS-20BA17]
Info: Unable to use EPCS device

By adding and modification *:\altera\14.1\nios2eds\bin\nios2-flash-override.txt

[EPCS-20BA17] # EPCS64N (lead-free)

sector_size = 65536

sector_count = 128


But,The question remains.
And the processing method, we can solve the problem in the quartus 13.1.
Now my company to adopt Quartus 14.1, how to solve the problem?
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Quantus II Programmer Auto Detect Problem with DE1-SoC

January 5, 2015, 1:09 am
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Hello,
I just bought a DE1-SoC. I wanted to program the board. While I am trying to program in the programmer window the "Auto Detect" remains inactive. I installed the driver (Blaster II) as told. The "Hardware Setup" window shoes DE1-SoC board. Unfortunately, The "auto detect" key is inactive or does not work. Can you please tell me why is it happening and how can I solve it.

Thank you

Momen
Attached Images
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Node Finder can find any nodes

January 5, 2015, 1:18 am
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Hello,

I have a problem with the Node Finder. I'm using Altera 13.1 SP1 Full Edition.
My Design is loaded an I can compile it etc. The design can be seen in RTL, Technology Viewer etc.

Actually I want to add a signal tap and add some nodes to it with the Node Finder. Now my problem.

The Node Finder can't find any nodes. I already played around with all the settings but he find NOTHING. Does anybody of you has an idea why this can be. Once I perform a search it takes up to 20sec to search for nodes and the following response I get. I can't find any signal Pre-Synthesis or Post or even In/output pins.



I'll also post here once I find the problem or a solution.

Thanks for any help, it is much appreciated.
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small area non volatile fpga

January 5, 2015, 1:38 am
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sir,

iam a design Engineer, searching for non volatile fpga with small body area(max size:10 x 10 mm)

guidance and support is required to start sketching the design in the paper.


Thanks.
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MAX10 (Select Internal Configuration mode with ERAM )

January 5, 2015, 5:22 am
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Hello,

In Quartus 14.0 SP1, i can compile my max10 sopc project ( Platform: BeMicro MAX 10)
all is running fine.

Now i switched to Quartus 14.1
In this Version i can't compile my project.

During compilation i get the error message:
"16031 Current Internal Configuration mode does not support memory initialization or ROM.
Select Internal Configuration mode with ERAM."

In Quartus 14.0 SP1 i can turn on "Enable ERAM Preload" in the Analysis and Synthesis settings.

But this Setting doesn't exist in Quartus 14.1

Are there any known workarounds ?
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[Nios II] Handle different sizes of SDRAM with the same software

January 5, 2015, 7:01 am
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Hi,

I use the nios ii processor in my application. For the moment, I use it with an 256Mb SYNCHRONOUS DRAM with 12 Row Address Input and 9 Column Address Input.

My application is evolving and I need a bigger memory. So I selected an 512Mb SYNCHRONOUS DRAM with 13 Row Address Input and 9 Column Address Input.

I often make software update (with bootloader) of my installed product base and I don't want to deal with two different software.

I can get the information of which RAM I have but I have not enough size in my EPCS to store two HW and software (to handle different sizes of RAM) + HW and software for the bootloader

Is it any way to select the RAM size in nios software at the code execution ?

If is not, have you any idea about my problem ?

Thanks for your help.
Sorry for my poor English.

Flandroid
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DE1-SoC No /dev/fpga0 device on LXDE or Ubuntu

January 5, 2015, 7:43 am
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I have been using the basic SD card image but now I need to move to using the LXDE or Ubuntu images supplied for use with the DE1-SoC.

However both these images do not feature a /dev/fpga0 device and so I am unable to program the FPGA from Linux (as opposed to u-boot).

How can I modify the LXDE or Ubuntu images so that:-
a. U-boot does not configure the FPGA
b. /dev/fpga0 is present allowing FPGA configuration from Linux

Any help / pointers appreciated . . .
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zero-delay buffer PLL issue

January 5, 2015, 11:29 am
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Hi,
I've recently started using Altera's PLLs for a Cyclone V project. I'm creating a PLL, with the IP Wizard, with zero-delay buffer (zdbfbclk) mode enabled. I want to use the zdbfbclk port to drive the clock signal I desire. However, I have not connected the single out clock port to anything. This results in the following warning:
Warning: OUTCLK port on the PLL is not properly connected on instance pllTdm:pllTdmI|pllTdm_0002:plltdm_inst|altera_pll: altera_pll_i|general[0].gpll. The output clock port on the PLL must be connected.

What is the proper way of connecting this port? Do I really need it? Am I correct in assuming the zdbfbclk can provide the clock signal I desire?
Any pointers/references to using this mode properly would be great.

Thanks in advance.
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Viewing Schematic

January 5, 2015, 1:58 pm
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Hi,

I have the latest wed edition installed on Win8.1 system. In schematic, the text is truncated on module pins or any signal pin. I cannot read the full names on signals. I believe something is out of wack with the fonts. I am at 2560x1440 resolution. Any tips would be appreciated.
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